中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

24 records (took 0.025 seconds)

    Row decoder for a non-volatile memory device, having reduced area occupation
    11.
    发明授权
    Row decoder for a non-volatile memory device, having reduced area occupation 有权

    公开(公告)号：US09767907B2

    公开(公告)日：2017-09-19

    申请号：US15083056

    申请日：2016-03-28

    Applicant: STMicroelectronics S.R.L.

    Inventor： Salvatore Polizzi ,  Giovanni Campardo

    IPC: G11C7/00 ,  G11C16/08 ,  G11C16/24 ,  G11C16/10 ,  G11C8/10

    CPC classification number: G11C16/08 ,  G11C8/10 ,  G11C16/10 ,  G11C16/24

    Abstract: A row decoder for a non-volatile memory device includes an input and pre-decoding module that receives address signals and generates pre-decoded address signals. A decoding module receives the pre-decoded address signals for generation on an output of decoded address signals. A driving module generates biasing signals for biasing wordlines of a memory array. The decoding module envisages a plurality of decoding stages, each of which carries out an operation of an OR logic combination between a first and a second predecoded address signal to be combined. The decoding module includes at least one first pass transistor for selectively transferring onto the output the one between the first and second predecoded address signals to be combined in a first operating condition. The decoding module includes at least one first pull-up transistor to selectively bring the output to a high state in at least one second operating condition.

    ROW DECODER FOR A NON-VOLATILE MEMORY DEVICE, HAVING REDUCED AREA OCCUPATION
    12.
    发明申请
    ROW DECODER FOR A NON-VOLATILE MEMORY DEVICE, HAVING REDUCED AREA OCCUPATION 有权

    公开(公告)号：US20170084334A1

    公开(公告)日：2017-03-23

    申请号：US15083056

    申请日：2016-03-28

    Applicant: STMicroelectronics S.R.L.

    Inventor： Salvatore Polizzi ,  Giovanni Campardo

    IPC: G11C16/08 ,  G11C16/10 ,  G11C16/24

    CPC classification number: G11C16/08 ,  G11C8/10 ,  G11C16/10 ,  G11C16/24

    Abstract: A row decoder for a non-volatile memory device includes an input and pre-decoding module that receives address signals and generates pre-decoded address signals. A decoding module receives the pre-decoded address signals for generation on an output of decoded address signals. A driving module generates biasing signals for biasing wordlines of a memory array. The decoding module envisages a plurality of decoding stages, each of which carries out an operation of an OR logic combination between a first and a second predecoded address signal to be combined. The decoding module includes at least one first pass transistor for selectively transferring onto the output the one between the first and second predecoded address signals to be combined in a first operating condition. The decoding module includes at least one first pull-up transistor to selectively bring the output to a high state in at least one second operating condition.

    Circuit and method for reading a memory cell of a non-volatile memory device
    14.
    发明授权
    Circuit and method for reading a memory cell of a non-volatile memory device 有权

    公开(公告)号：US10249373B2

    公开(公告)日：2019-04-02

    申请号：US15862397

    申请日：2018-01-04

    Applicant: STMicroelectronics S.r.l.

    Inventor： Giovanni Campardo ,  Salvatore Polizzi

    IPC: G11C11/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C7/12 ,  G11C7/18 ,  G11C16/24 ,  G11C16/28

    Abstract: A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.

    Row decoder for a non-volatile memory device, and non-volatile memory device
    15.
    发明授权
    Row decoder for a non-volatile memory device, and non-volatile memory device 有权

    公开(公告)号：US09679655B2

    公开(公告)日：2017-06-13

    申请号：US15140770

    申请日：2016-04-28

    Applicant: STMicroelectronics S.r.l

    Inventor： Salvatore Polizzi ,  Giovanni Campardo

    IPC: G11C16/08 ,  G11C16/10 ,  G11C16/32

    CPC classification number: G11C16/10 ,  G11C5/145 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

    Abstract: A non-volatile memory device includes a memory array having memory cells arranged in wordlines and receiving a supply voltage. A row decoder includes an input and pre-decoding module, which is configured to receive address signals and generate pre-decoded address signals at low voltage, in the range of the supply voltage. A driving module is configured to generate biasing signals for biasing the wordlines of the memory array starting from decoded address signals, which are a function of the pre-decoded address signals, at high voltage and in the range of a boosted voltage higher than the supply voltage. A processing module is configured to receive the pre-decoded address signals and to jointly execute an operation of logic combination and an operation of voltage boosting of the pre-decoded address signals for generation of the decoded address signals.

    PHASE-CHANGE MEMORY AND METHODS FOR MANUFACTURING, PROGRAMMING, AND READING THEREOF
    16.
    发明申请
    PHASE-CHANGE MEMORY AND METHODS FOR MANUFACTURING, PROGRAMMING, AND READING THEREOF 有权

    公开(公告)号：US20220199900A1

    公开(公告)日：2022-06-23

    申请号：US17644942

    申请日：2021-12-17

    Applicant: STMicroelectronics S.r.l.

    Inventor： Giovanni Campardo ,  Massimo Borghi

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24 ,  H01L23/528

    Abstract: A phase-change memory (PCM) includes a semiconductor body housing a selection transistor; a electrical-insulation body disposed over the semiconductor body; a conductive region, extending through the electrical-insulation body, electrically coupled to the selection transistor; and a plurality of heater elements in the electrical-insulation body. Each of the plurality of heater elements include a first end in electrical contact with a respective portion of the conductive region and a second end that extends away from the conductive region. The PCM further includes a plurality of phase-change elements extending in the electrical-insulation body and including data storage regions, where each of the data storage regions being electrically and thermally coupled to one respective heater element at the second end of the respective heater element.

    PHASE CHANGE MEMORY DEVICE AND METHOD OF PROGRAMMING A PHASE CHANGE MEMORY DEVICE
    17.
    发明申请
    PHASE CHANGE MEMORY DEVICE AND METHOD OF PROGRAMMING A PHASE CHANGE MEMORY DEVICE 有权

    公开(公告)号：US20210166757A1

    公开(公告)日：2021-06-03

    申请号：US17099257

    申请日：2020-11-16

    Applicant: STMicroelectronics S.r.l.

    Inventor： Giovanni Campardo ,  Massimo Borghi ,  Paola Zuliani ,  Marco Barboni

    IPC: G11C13/00 ,  H01L45/00

    Abstract: An embodiment phase-change memory device includes a memory array provided with a plurality of phase-change memory cells, each having a body made of phase-change material and a first state, in which the phase-change material is completely in an amorphous phase, and at least one second state, in which the phase-change material is partially in the amorphous phase and partially in a crystalline phase. A programming-pulse generator applies to the memory cells rectangular dynamic-programming pulses having an amplitude and a duration calibrated for switching the memory cells from the first state to the second state.

Patent Agency Ranking