中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

24 records (took 0.014 seconds)

    NON-VOLATILE MEMORY DEVICE, IN PARTICULAR PHASE CHANGE MEMORY, AND READING METHOD
    1.
    发明申请
    NON-VOLATILE MEMORY DEVICE, IN PARTICULAR PHASE CHANGE MEMORY, AND READING METHOD 审中-公开

    公开(公告)号：US20190341103A1

    公开(公告)日：2019-11-07

    申请号：US16393115

    申请日：2019-04-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Giovanni Campardo ,  Roberto Annunziata ,  Paola Zuliani

    IPC: G11C13/00

    Abstract: A non-volatile memory device has a circuit branch associated to a bit line connected to a memory cell. When the memory cell is read, in a precharging step, the bit line is precharged. In a characteristic shift step, the memory cell is activated, and a current source is activated to supply a shift current to the first bit line and cause the bit line to charge or discharge on the basis of the datum stored in the memory cell. In a detection step, the current source is deactivated, the memory cell is decoupled, and the bit line is coupled to an input of a comparator stage that compares the voltage on the bit line with a reference voltage to supply an output signal indicating a datum stored in the memory cell.

    Circuit and method for reading a memory cell of a non-volatile memory device
    6.
    发明授权
    Circuit and method for reading a memory cell of a non-volatile memory device 有权

    公开(公告)号：US10249373B2

    公开(公告)日：2019-04-02

    申请号：US15862397

    申请日：2018-01-04

    Applicant: STMicroelectronics S.r.l.

    Inventor： Giovanni Campardo ,  Salvatore Polizzi

    IPC: G11C11/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C7/12 ,  G11C7/18 ,  G11C16/24 ,  G11C16/28

    Abstract: A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.

    Row decoder for a non-volatile memory device, and non-volatile memory device
    7.
    发明授权
    Row decoder for a non-volatile memory device, and non-volatile memory device 有权

    公开(公告)号：US09679655B2

    公开(公告)日：2017-06-13

    申请号：US15140770

    申请日：2016-04-28

    Applicant: STMicroelectronics S.r.l

    Inventor： Salvatore Polizzi ,  Giovanni Campardo

    IPC: G11C16/08 ,  G11C16/10 ,  G11C16/32

    CPC classification number: G11C16/10 ,  G11C5/145 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

    Abstract: A non-volatile memory device includes a memory array having memory cells arranged in wordlines and receiving a supply voltage. A row decoder includes an input and pre-decoding module, which is configured to receive address signals and generate pre-decoded address signals at low voltage, in the range of the supply voltage. A driving module is configured to generate biasing signals for biasing the wordlines of the memory array starting from decoded address signals, which are a function of the pre-decoded address signals, at high voltage and in the range of a boosted voltage higher than the supply voltage. A processing module is configured to receive the pre-decoded address signals and to jointly execute an operation of logic combination and an operation of voltage boosting of the pre-decoded address signals for generation of the decoded address signals.

    Integrated semiconductor device and process for manufacturing an integrated semiconductor device
    10.
    发明授权
    Integrated semiconductor device and process for manufacturing an integrated semiconductor device 有权

    公开(公告)号：US11069587B2

    公开(公告)日：2021-07-20

    申请号：US16905486

    申请日：2020-06-18

    Applicant: STMicroelectronics S.r.l.

    Inventor： Giovanni Campardo ,  Marco Omar Ghidoni

    IPC: H01L23/13 ,  H01L23/00

    Abstract: An integrated semiconductor device and a method for manufacturing the integrated semiconductor device are disclosed. In an embodiment an integrated semiconductor device includes a supporting substrate having a first substrate face and a second substrate face opposite to the first substrate face, a semiconductor die having a first die face coupled to the first substrate face of the supporting substrate, the first die face including first die contact pads, wherein the supporting substrate has at least one through opening, wherein the first die contact pads are arranged facing the through opening, and wherein the supporting substrate comprises first substrate contact pads connected by first bonding wires to the respective first die contact pads through the through opening.

Patent Agency Ranking