-
11.发明授权Driving stage for phase change non-volatile memory devices provided with auto-calibration feature 有权具有自动校准功能的相变非易失性存储器件的驱动级公开(公告)号：US08942033B2
公开(公告)日：2015-01-27
申请号：US13774181
申请日：2013-02-22
Applicant: STMicroelectronics S.R.L.
Inventor： Antonino Conte , Kailash Khairnar , FrancescoNino Mammoliti
CPC classification number: G11C13/0004 , G11C5/145 , G11C5/147 , G11C13/0038 , G11C13/0069
Abstract: A driving stage for a phase change non-volatile memory device may include an output driving unit, which supplies an output driving current during programming of a memory cell, a driving-control unit, which receives an input current and generates a first control signal for controlling supply of the output driving current in such a way that a value thereof has a desired relation with the input current, and a level-shifter element, which carries out a level shift of a voltage of the first control signal for supplying to the output driving unit a second control signal, having a voltage value that is increased with respect to, and is a function of, the first control signal. A calibration unit may carry out an operation of updating of the value of a shift voltage across the level-shifter element, as the value of the input current varies.
Abstract translation: 用于相变非易失性存储器件的驱动级可以包括输出驱动单元，其在存储单元的编程期间提供输出驱动电流;驱动控制单元，其接收输入电流并产生第一控制信号， 控制输出驱动电流的供给，使得其值与输入电流具有期望的关系;电平移动元件，其执行用于提供给输出的第一控制信号的电压的电平偏移 驱动单元具有第二控制信号，其具有相对于第一控制信号增加并且是第一控制信号的函数的电压值。 校准单元可以执行更新跨越电平移位器元件的移位电压的值的操作，因为输入电流的值变化。
-
公开(公告)号：US12057180B2
公开(公告)日：2024-08-06
申请号：US17934102
申请日：2022-09-21
Inventor： Francesco La Rosa , Antonino Conte , Francois Maugain
CPC classification number: G11C16/3445 , G11C16/14 , G11C16/26 , G11C16/3459 , G11C16/349 , H10B41/30 , H10B41/40
Abstract: In an embodiment a non-volatile memory device includes a memory array having a plurality of memory cells, a control unit operatively coupled to the memory array, a biasing stage controllable by the control unit and configured to apply a biasing configuration to the memory cells to perform a memory operation and a reading stage coupled to the memory array and controllable by the control unit, the reading stage configured to verify whether the memory operation has been successful based on a verify level, wherein the control unit is configured to adaptively modify a value of the verify level based on an ageing of the memory cells.
-
公开(公告)号：US20240153553A1
公开(公告)日：2024-05-09
申请号：US18406097
申请日：2024-01-06
Inventor： Antonino Conte , Alin Razafindraibe , Francesco Tomaiuolo , Thibault Mortier
IPC: G11C13/00
CPC classification number: G11C13/0028 , G11C13/0004 , G11C13/003 , G11C2213/79
Abstract: In an embodiment, a non-volatile memory device is proposed. The device includes a plurality of local pull-up stages distributed along a group of memory portions in a memory array. Each local pull-up stage includes, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type. The local pull-up transistors of each local pull-up are configured to locally decouple the corresponding wordline from a node at a first reference potential in response to a wordline that extends through the group of memory portions being selected, and locally couple the corresponding wordline to the node at the first reference potential in response to all the wordlines that extend through the group of memory portions being deselected to restore locally a deselection voltage on a wordline previously selected.
-
公开(公告)号：US11526190B2
公开(公告)日：2022-12-13
申请号：US16868799
申请日：2020-05-07
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Conte
IPC: G05F3/26
Abstract: An apparatus includes a current mirror coupled to an output of an amplifier through control switches, a plurality of capacitors, each of which is coupled to a common node of a leg of the current mirror and a corresponding control switch, a first dipole coupled to a first input of an amplifier, a second dipole coupled to a second input of the amplifier, a third dipole coupled to an output of the apparatus configured to generate the bandgap reference voltage, and groups of switches coupled between the current mirror and the dipoles.
-
公开(公告)号：US10281512B2
公开(公告)日：2019-05-07
申请号：US15387370
申请日：2016-12-21
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Antonino Conte , Enrico Castaldo , Raul Andres Bianchi , Francesco La Rosa
Abstract: A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.
-
Patent Agency Ranking
公开(公告)号：US20190108886A1
公开(公告)日：2019-04-11
申请号：US16145734
申请日：2018-09-28
Applicant: STMicroelectronics S.r.l.
Inventor： Carmelo Paolino , Antonino Conte , Anna Rita Maria Lipani
CPC classification number: G11C16/28 , G11C7/065 , G11C7/08 , G11C13/004 , G11C13/0061 , G11C16/0408 , G11C16/24 , G11C2013/0042 , G11C2013/0045 , G11C2013/0054 , G11C2207/063
Abstract: A sense-amplifier circuit can be used with a non-volatile memory device having a memory array with memory cells arranged in word lines and bit lines and coupled to respective source lines. The circuit has a first circuit branch and a second circuit branch, which receive on a respective first comparison input and second comparison input, during a reading step of a datum stored in a memory cell, a cell current from the bit line associated to the memory cell and a reference current, from a reference bit line in a differential reading operation or from a current-reference generator in a single-ended reading operation. The first and second circuit branches generate, during the datum-reading step, a first output voltage and a second output voltage, as a function of the difference between the cell current and the reference current.
-
公开(公告)号：US09972394B2
公开(公告)日：2018-05-15
申请号：US15476003
申请日：2017-03-31
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Conte , Carmelo Paolino , Maurizio Francesco Perroni , Salvatore Polizzi
CPC classification number: G11C16/12 , G11C8/08 , G11C13/0004 , G11C16/08 , G11C16/20 , G11C16/26 , H03K3/356113 , H03K19/018521
Abstract: A level shifter circuit is designed to shift an input signal that switches within a first voltage range to supply an output signal that switches within a second voltage range, higher than the first voltage range. A first inverter stage has an input receiving the input signal and also has an output. A first capacitive element is connected between the output of the first input inverter stage and a first holding node. A latch stage is connected between the first holding node and a second holding node that is coupled to an output terminal, on which the output signal is present. The first input inverter stage is designed to operate in the first voltage range, and the latch stage is designed to operate in the second voltage range.
-
18.发明授权公开(公告)号：US09679618B2
公开(公告)日：2017-06-13
申请号：US14703173
申请日：2015-05-04
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Antonino Conte , Mario Micciche′ , SantiNunzioAntonino Pagano
CPC classification number: G11C7/062 , G11C7/1051 , G11C7/12 , G11C16/24 , G11C16/28 , G11C2207/002
Abstract: A sense structure may include sense amplifiers each having measuring and reference terminals for receiving a measuring and a reference current, respectively, output circuitry for providing an output voltage based upon the measuring and reference currents, and voltage regulating circuitry in cascode configuration for regulating a voltage at the measuring and reference terminals. The regulating circuitry may include measuring and regulating transistors and a reference regulating transistor having a first conduction terminal coupled with the measuring terminal and with the reference terminal, respectively, a second conduction terminal coupled with the output circuitry and a control terminal coupled with a biasing terminal. Biasing circuitry is for providing a biasing voltage to the biasing terminal, and common regulating circuitry is for regulating the biasing voltage. Each sense amplifier may also include local regulating circuitry for regulating the biasing voltage applied to the biasing terminal.
-
公开(公告)号：US11908514B2
公开(公告)日：2024-02-20
申请号：US17667080
申请日：2022-02-08
Inventor： Antonino Conte , Alin Razafindraibe , Francesco Tomaiuolo , Thibault Mortier
IPC: G11C13/00
CPC classification number: G11C13/0028 , G11C13/003 , G11C13/0004 , G11C2213/79
Abstract: In an embodiment, a non-volatile memory device includes a memory array including a plurality of memory portions, each memory portion having a respective plurality of memory cells arranged in rows and columns, wherein the memory portions are arranged in groups, each group of memory portions having a plurality of respective memory portions arranged in a row and a plurality of respective wordlines that extend through the respective memory portions, and wherein the memory cells of the memory portions of the group are coupled to the respective wordlines and a row decoder including a pre-decoding stage configured to execute a selection, in which it selects a wordline that extends through a group of memory portions and deselects other wordlines that extend through the group of memory portions, and a subsequent deselection, in which it deselects all the wordlines that extend through the group of memory portions, wherein the row decoder further includes, for each group of memory portions, a shared pull-up stage configured to decouple from or couple to a node at a first reference potential each wordline that extends through the group of memory portions, when the wordline is respectively selected or deselected, so as to impose on each wordline, when deselected, a deselection voltage, a plurality of pull-down stages distributed along the group of memory portions, each pull-down stage being configured to locally couple each wordline that extends through the group of memory portions, when selected, to a node at a second reference potential, so as to impose locally a selection voltage on the wordline, wherein each pull-down stage is further configured to locally decouple from the node at the second reference potential each wordline that extends through the group of memory portions, when deselected; and a number of local pull-up stages distributed along the group of memory portions, each local pull-up stage having, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type.
-
20.发明申请公开(公告)号：US20230021601A1
公开(公告)日：2023-01-26
申请号：US17814442
申请日：2022-07-22
Applicant: STMicroelectronics S.r.l.
Inventor： Agatino Massimo Maccarrone , Antonino Conte , Francesco Tomaiuolo , Michelangelo Pisasale , Marco Ruta
IPC: G11C13/00
Abstract: In an embodiment a circuit includes a plurality of memory cells, wherein each memory cell includes a phase-change memory storage element coupled in series with a respective current-modulating transistor between a supply voltage node and a reference voltage node, the current-modulating transistors being configured to receive a drive signal at a control terminal and to inject respective programming currents into the respective phase-change memory storage element as a function of the drive signal, a driver circuit configured to produce the drive signal at a common control node, wherein the common control node is coupled to the control terminals of the current-modulating transistors, the drive signal modulating the programming currents to produce SET programming current pulses and RESET programming current pulses and at least one current generator circuit configured to inject a compensation current into the common control node in response to the current-modulating transistors injecting the programming currents into the respective phase-change memory storage elements.
-
-
-
-
-
-
-
-
-
Search Results
61
records
(took 0.046 seconds)
