公开(公告)号：US10770306B2

公开(公告)日：2020-09-08

申请号：US16240044

申请日：2019-01-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Bar ,  Francois Leverd ,  Delia Ristoiu

IPC: H01L21/3065 ,  H01L21/311 ,  H01L21/308 ,  H01L21/02 ,  G02B6/36 ,  G02B6/42

Abstract: A cavity is etched in a stack of layers which includes a first layer made of a first material and a second layer made of a second material. To etch the cavity, a first etch mask having a first opening is formed over the stack of layer. The stack of layers is then etched through the first opening to a depth located in the second layer. A second mask having a second opening, the dimensions of which are smaller, in top view, than the first opening, is formed over the stack of layer. The second opening is located, in top view, opposite the area etched through the first opening. The second layer is then etched through the second opening to reach the first layer. The etch method used is configured to etch the second material selectively over the first material.

公开(公告)号：US09673088B2

公开(公告)日：2017-06-06

申请号：US14970792

申请日：2015-12-16

Applicant: STMicroelectronics SA

Inventor： Sylvain Joblot ,  Pierre Bar

IPC: H01L21/768 ,  G02B6/12 ,  H01P11/00 ,  H01L21/762 ,  H01L21/48

CPC classification number: H01L21/76831 ,  G02B6/12 ,  H01L21/4846 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/66 ,  H01P11/003

Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.

公开(公告)号：US20160204031A1

公开(公告)日：2016-07-14

申请号：US15074130

申请日：2016-03-18

Applicant: STMicroelectronics SA

Inventor： Sylvain Joblot ,  Pierre Bar

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/66

CPC classification number: H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01P3/003 ,  H01P3/006 ,  H01P11/003 ,  H01L2924/00

Abstract: In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.

公开(公告)号：US20160197048A1

公开(公告)日：2016-07-07

申请号：US15070046

申请日：2016-03-15

Applicant: STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Pierre Bar ,  Laurent Dussopt ,  Jean-Francois Carpentier

IPC: H01L23/66 ,  H01Q19/10 ,  H01L23/528 ,  H04B1/3827 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01Q13/10 ,  H01L23/522

CPC classification number: H01L23/66 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/15788 ,  H01Q1/243 ,  H01Q1/50 ,  H01Q9/0457 ,  H01Q13/106 ,  H01Q19/10 ,  H01Q23/00 ,  H04B1/3833 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941

Abstract: A three-dimensional integrated structure includes a support element, an interface device connected to the support element by a first electrically conductive connection, and an integrated circuit arranged between the support element and the interface device and connected to the interface device by a second electrically conductive connection. A filler region is positioned between the second electrically conductive connection and between the interface device and the integrated circuit. An antenna is distributed over the interface device and the integrated circuit and has a radiating element electromagnetically coupled with an excitation element through the interconnection of a slot.

Abstract translation: 三维集成结构包括支撑元件，通过第一导电连接连接到支撑元件的接口装置，以及布置在支撑元件和接口装置之间并且通过第二导电连接到接口装置的集成电路 连接。 填充区域位于第二导电连接之间以及接口装置和集成电路之间。 天线分布在接口装置和集成电路上，并且具有通过插槽的互连与激励元件电磁耦合的辐射元件。

公开(公告)号：US09818646B2

公开(公告)日：2017-11-14

申请号：US15583342

申请日：2017-05-01

Applicant: STMicroelectronics SA

Inventor： Sylvain Joblot ,  Pierre Bar

IPC: G02B6/12 ,  H01L21/768 ,  H01L21/48 ,  H01L21/762 ,  H01L23/66 ,  H01P11/00

CPC classification number: H01L21/76831 ,  G02B6/12 ,  H01L21/4846 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/66 ,  H01P11/003

Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.

公开(公告)号：US20170236753A1

公开(公告)日：2017-08-17

申请号：US15583342

申请日：2017-05-01

Applicant: STMicroelectronics SA

Inventor： Sylvain Joblot ,  Pierre Bar

IPC: H01L21/768 ,  H01P11/00 ,  H01L23/66 ,  H01L21/48 ,  H01L21/762

CPC classification number: H01L21/76831 ,  G02B6/12 ,  H01L21/4846 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/66 ,  H01P11/003

Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.

公开(公告)号：US09646914B2

公开(公告)日：2017-05-09

申请号：US14958623

申请日：2015-12-03

Applicant: STMicroelectronics SA

Inventor： Pierre Bar ,  Perceval Coudrain

IPC: H01L23/52 ,  H01L23/373 ,  H01L21/48 ,  H01L23/498 ,  H01L23/473 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/373 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/76898 ,  H01L23/473 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589

Abstract: A three-dimensional integrated structure includes a first and a second element each having an interconnection part formed by metallization levels encased in an insulating region. The first and second elements are attached to one another by the respective interconnection parts. The first element includes an electrical connection via passing through a substrate. A thermal cooling system includes at least one cavity having a first part located in the insulating region of the interconnection part of the first element and a second part located in the insulating region of the interconnection part of the second element and at least one through channel extending from a rear face of the first element to open into the at least one cavity.

公开(公告)号：US20160343638A1

公开(公告)日：2016-11-24

申请号：US14958623

申请日：2015-12-03

Applicant: STMicroelectronics SA

Inventor： Pierre Bar ,  Perceval Coudrain

IPC: H01L23/373 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/373 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/76898 ,  H01L23/473 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589

Abstract: A three-dimensional integrated structure includes a first and a second element each having an interconnection part formed by metallization levels encased in an insulating region. The first and second elements are attached to one another by the respective interconnection parts. The first element includes an electrical connection via passing through a substrate. A thermal cooling system includes at least one cavity having a first part located in the insulating region of the interconnection part of the first element and a second part located in the insulating region of the interconnection part of the second element and at least one through channel extending from a rear face of the first element to open into the at least one cavity.

Abstract translation: 三维集成结构包括第一和第二元件，每个元件具有通过金属化等级封装在绝缘区域中形成的互连部件。 第一和第二元件通过相应的互连部件彼此附接。 第一元件包括通过基板的电连接。 热冷却系统包括至少一个腔，其具有位于第一元件的互连部分的绝缘区域中的第一部分和位于第二元件的互连部分的绝缘区域中的第二部分，以及至少一个贯穿通道 从第一元件的后表面开始进入至少一个空腔。

公开(公告)号：US09324612B2

公开(公告)日：2016-04-26

申请号：US13899326

申请日：2013-05-21

Applicant: STMicroelectronics SA

Inventor： Sylvain Joblot ,  Pierre Bar

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/768 ,  H01P3/00 ,  H01P11/00

CPC classification number: H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01P3/003 ,  H01P3/006 ,  H01P11/003 ,  H01L2924/00

Abstract: In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.

Abstract translation: 在一个实施例中，公开了一种用于在包括通孔和共面线的半导体衬底中制造集成电路的方法，包括以下步骤：形成有源部件和一组前金属化层; 同时从衬底a的后表面通过通孔和穿过衬底穿过其高度的至少50％的沟槽; 用导电材料涂覆壁和孔的底部和沟槽; 并用绝缘填充材料填充孔和沟槽; 并且在沟槽的前面并与其平行地形成在衬底的后表面上延伸的共面线，使得共面线的横向导体电连接到涂覆沟槽的壁的导电材料。

公开(公告)号：US20160097898A1

公开(公告)日：2016-04-07

申请号：US14970792

申请日：2015-12-16

Applicant: STMicroelectronics SA

Inventor： Sylvain Joblot ,  Pierre Bar

IPC: G02B6/12 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L21/76831 ,  G02B6/12 ,  H01L21/4846 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/66 ,  H01P11/003

Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.

Abstract translation: 集成电路包括绝缘体上硅晶片和互连层，其为在支撑体的顶侧上方形成的共面波导提供支撑。 穿通硅通孔由支撑体的背面形成并穿过绝缘体上硅晶片以到达互连层。 从共面波导下方的支撑体的背面形成沟槽。 沟槽在共面波导的至少整个长度上延伸。 沟槽穿过绝缘体上硅晶片以到达互连层，并且可以具有与穿硅通孔基本相同的深度。