公开(公告)号：US10790358B2

公开(公告)日：2020-09-29

申请号：US16515412

申请日：2019-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moorym Choi ,  Bongyong Lee ,  Junhee Lim

IPC: H01L27/00 ,  H01L29/10 ,  H01L29/78 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device includes common source regions, an electrode structure between the common source regions, first channel structures penetrating the electrode structure, and second channel structures between the first channel structures and penetrating the electrode structures. The electrode structure includes electrodes vertically stacked on a substrate. The first channel structures include a first semiconductor pattern and a first vertical insulation layer. The second channel structures include a second vertical insulation layer surrounding a second semiconductor pattern. The second vertical insulation layer has a bottom surface lower than a bottom surface of the first vertical insulation layer.

公开(公告)号：US09042175B2

公开(公告)日：2015-05-26

申请号：US13753677

申请日：2013-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaesung Sim ,  Bongyong Lee

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/06 ,  G11C7/04 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C2216/14

Abstract: Disclosed is a nonvolatile memory device which includes a memory cell connected to a bit line and a word line; a page buffer electrically connected to the bit line and sensing data stored in the memory cell; and a control logic controlling the page buffer to vary a develop time of the bit line or a sensing node connected to the bit line according to a current temperature during a read operation.

Abstract translation: 公开了一种非易失性存储器件，其包括连接到位线和字线的存储单元; 电位连接到位线并感测存储在存储单元中的数据的页缓冲器; 以及控制逻辑控制页缓冲器，以在读操作期间根据当前温度来改变位线或连接到位线的感测节点的显影时间。

公开(公告)号：US20230371265A1

公开(公告)日：2023-11-16

申请号：US18136993

申请日：2023-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongyong Lee ,  Myunghun Woo ,  Yongseok Kim

IPC: H10B51/20 ,  H10B51/10 ,  H01L29/417 ,  H01L29/51

CPC classification number: H10B51/20 ,  H10B51/10 ,  H01L29/41725 ,  H01L29/516

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes: a conductive layer on a substrate; an insulating isolation layer on the conductive layer; a stack structure on the insulating isolation layer, the stack structure including a plurality of source/drain contact layers and a plurality of gate electrode layers alternately provided along a first direction, perpendicular to an upper surface of the substrate; a vertical channel layer extending through the stack structure and the insulating isolation layer, wherein the vertical channel layer is in contact with each of the plurality of source/drain contact layers, and is connected to the conductive layer; and a gate insulating layer between each of the plurality of gate electrode layers and the vertical channel layer.

公开(公告)号：US11778825B2

公开(公告)日：2023-10-03

申请号：US17702967

申请日：2022-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongyong Lee ,  Taehun Kim ,  Minkyung Bae ,  Myunghun Woo ,  Doohee Hwang

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

Abstract: A vertical semiconductor layer includes a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.

公开(公告)号：US20230269941A1

公开(公告)日：2023-08-24

申请号：US18095576

申请日：2023-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongyong Lee ,  Yukio Hayakawa ,  Taeyoung Kim ,  Hyunmog Park ,  Siyeon Cho

IPC: H10B43/27 ,  H10B43/35 ,  H10B43/10 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  G11C16/14

CPC classification number: H10B43/27 ,  H10B43/35 ,  H10B43/10 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  G11C16/14

Abstract: A semiconductor device includes a source structure, gate electrodes spaced apart from each other and stacked in a first direction, perpendicular to an upper surface of the source structure, and a channel structure extending through the gate electrodes in the first direction, and including a dielectric layer, a charge storage layer, a tunneling layer, a channel layer, and a buried semiconductor layer. The dielectric layer is between the gate electrodes and the charge storage layer. The tunneling layer is between charge storage layer and the channel layer. The channel layer is between the tunneling layer and the buried semiconductor layer. An outer surface of a lower portion of the channel layer is in contact with the source structure, and the dielectric layer includes a ferroelectric material, the channel layer includes an oxide semiconductor material, and the buried semiconductor layer includes silicon (Si).

公开(公告)号：US20220344244A1

公开(公告)日：2022-10-27

申请号：US17571874

申请日：2022-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyojoon Ryu ,  Bongyong Lee ,  Heesuk Kim ,  Junhee Lim ,  Sangyoun Jo ,  Kohji Kanamori ,  Jeehoon Han

IPC: H01L23/48 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device includes a first structure and a second structure thereon. The first structure includes a substrate, circuit elements on the substrate, a lower interconnection structure electrically connected to the circuit elements, and lower bonding pads, which are electrically connected to the lower interconnection structure. The second structure includes a stack structure including: gate electrodes and interlayer insulating layers, which are alternately stacked and spaced apart in a vertical direction; a plate layer that extends on the stack structure; channel structures within the stack structure, separation regions, which penetrate at least partially through the stack structure, and upper bonding pads, which are electrically connected to the gate electrodes and the channel structures, and are bonded to corresponding ones of the lower bonding pads.

公开(公告)号：US11315946B2

公开(公告)日：2022-04-26

申请号：US16838106

申请日：2020-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongyong Lee ,  Taehun Kim ,  Minkyung Bae ,  Myunghun Woo ,  Doohee Hwang

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11524

Abstract: A vertical semiconductor layer includes a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.

公开(公告)号：US08942042B2

公开(公告)日：2015-01-27

申请号：US13772868

申请日：2013-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Jeong Lee ,  Bongyong Lee ,  Dongchan Kim ,  Jaesung Sim

IPC: G11C16/04 ,  G11C16/10 ,  H01L27/115 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3409 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method of adjusting a threshold voltage of a ground selection transistor in a nonvolatile memory device includes providing a first voltage to a gate of a first ground selection transistor in a read operation and providing a second voltage to a gate of a second ground selection transistor in the read operation. The nonvolatile memory device includes at least one string, the string having string selection transistors, memory cells and the first and second ground selection transistors connected in series and stacked on a substrate.

Abstract translation: 一种在非易失性存储器件中调整接地选择晶体管的阈值电压的方法包括：在读取操作中向第一接地选择晶体管的栅极提供第一电压，并向第二接地选择晶体管的栅极提供第二电压， 读操作。 非易失性存储器件包括至少一个串，串具有串选择晶体管，存储单元以及串联连接并堆叠在基板上的第一和第二接地选择晶体管。