公开(公告)号：US09337125B2

公开(公告)日：2016-05-10

申请号：US13926616

申请日：2013-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-hwa Park ,  Kwang-jin Moon ,  Byung-lyul Park

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L25/065 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552

CPC classification number: H01L23/481 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/49827 ,  H01L23/53238 ,  H01L23/552 ,  H01L25/0657 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/13 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Integrated circuit devices are provided. The integrated circuit devices may include a via structure including a conductive plug, a conductive barrier layer spaced apart from the conductive plug, and an insulating layer between the conductive plug and conductive barrier layer. Related methods of forming integrated circuit devices are also provided.

Abstract translation: 提供集成电路设备。 集成电路器件可以包括通孔结构，其包括导电插塞，与导电插塞间隔开的导电阻挡层，以及在导电插塞和导电阻挡层之间的绝缘层。 还提供了形成集成电路器件的相关方法。

公开(公告)号：US08872354B2

公开(公告)日：2014-10-28

申请号：US13850918

申请日：2013-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han Kyu-hee ,  Sang-hoon Ahn ,  Jang-hee Lee ,  Jong-min Beak ,  Kyoung-hee Kim ,  Byung-lyul Park ,  Byung-hee Kim

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76898 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: A method of forming through silicon vias (TSVs) uses a low-k dielectric material as a via insulating layer to thereby improve step coverage and minimize resistive capacitive (RC) delay. To this end, the method includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.

Abstract translation: 通过硅通孔（TSV）形成的方法使用低k电介质材料作为通孔绝缘层，从而提高步骤覆盖并最小化电阻电容（RC）延迟。 为此，该方法包括在半导体衬底中形成初级通孔，在初级通孔中沉积低k电介质材料，通过在主通孔中蚀刻低k电介质形成次通孔， 同时形成低k电介质层的通孔绝缘层和金属间介电层的方式。 通孔绝缘层由侧壁上的低k电介质材料和限定初级通孔的衬底的底表面形成，并且金属介电层形成在衬底的上表面上。 然后在包括在二次通孔中的基板上形成金属层，并且从半导体基板的上表面选择性地去除金属层。

公开(公告)号：US09461007B2

公开(公告)日：2016-10-04

申请号：US14796506

申请日：2015-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-ho Chun ,  Pil-kyu Kang ,  Byung-lyul Park ,  Jae-hwa Park ,  Ju-il Choi

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/532 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L23/3192 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/05 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/08145 ,  H01L2224/80862 ,  H01L2224/80895 ,  H01L2224/80905 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2924/06 ,  H01L2924/0695 ,  H01L2924/07025 ,  H01L2224/80 ,  H01L2924/00014

Abstract: A wafer-to-wafer bonding structure may include: a first wafer including a first insulating layer on a first substrate and on a first copper (Cu) pad that penetrates the first insulating layer and has portions protruding from an upper surface of the first insulating layer, and a first barrier metal layer on a lower surface and sides of the first Cu pad; a second wafer including a second insulating layer on a second substrate and on a second copper (Cu) pad that penetrates the second insulating layer, has portions protruding from an upper surface of the second insulating layer, and is bonded to the first Cu pad, and a second barrier metal layer on a lower surface and sides of the second Cu pad; and a polymer layer covering protruding sides of the first and second barrier metal layers and disposed between the first and second wafers.

Abstract translation: 晶片到晶片接合结构可以包括：第一晶片，其包括在第一基板上的第一绝缘层和穿过第一绝缘层的第一铜（Cu）焊盘，并且具有从第一绝缘层的上表面突出的部分 层和第一Cu衬垫的下表面和侧面上的第一阻挡金属层; 包括在第二基板上的第二绝缘层和穿过第二绝缘层的第二铜（Cu）焊盘上的第二晶片具有从第二绝缘层的上表面突出的部分并且接合到第一Cu焊盘， 以及在所述第二Cu垫的下表面和侧面上的第二阻挡金属层; 以及覆盖第一和第二阻挡金属层的突出侧并设置在第一和第二晶片之间的聚合物层。

公开(公告)号：US20130264720A1

公开(公告)日：2013-10-10

申请号：US13733923

申请日：2013-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-ho Chun ,  Byung-lyul Park ,  Hyun-soo Chung ,  Gil-heyun Choi ,  Son-kwan Hwang

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/768 ,  H01L21/76841 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/544 ,  H01L24/03 ,  H01L24/81 ,  H01L25/065 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05025 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8185 ,  H01L2924/00014 ,  H01L2924/06 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.

Abstract translation: 包括通过硅通孔（TSV）的半导体芯片，其中可以防止TSV弯曲，并且可以简化制造半导体芯片的方法，以及制造半导体芯片的方法。 半导体芯片包括具有第一表面和第二表面的硅衬底; 多个TSV，其穿透硅衬底并突出在硅衬底的第二表面上方; 形成在硅衬底的第二表面上的聚合物图案层围绕每个TSV的突出部分的侧表面，并且包括平坦的第一部分和在第一部分上方突出的第二部分; 以及形成在聚合物图案层上并覆盖从聚合物图案层露出的每个TSV的一部分的电镀垫。