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    METHOD OF FORMING THROUGH SILICON VIA OF SEMICONDUCTOR DEVICE USING LOW-K DIELECTRIC MATERIAL
    8.
    发明申请
    METHOD OF FORMING THROUGH SILICON VIA OF SEMICONDUCTOR DEVICE USING LOW-K DIELECTRIC MATERIAL 有权
    使用低K电介质材料的半导体器件通过硅形成的方法

    公开(公告)号：US20130228936A1

    公开(公告)日：2013-09-05

    申请号：US13850918

    申请日：2013-03-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyu-hee Han ,  Sang-hoon Ahn ,  Jang-hee Lee ,  Jong-min Beak ,  Kyoung-hee Kim ,  Byung-lyul Park ,  Byung-hee Kim

    IPC: H01L23/48

    CPC classification number: H01L23/481 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76898 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2924/00014 ,  H01L2224/05552

    Abstract: A method of forming through silicon vias (TSVs) uses a low-k dielectric material as a via insulating layer to thereby improve step coverage and minimize resistive capacitive (RC) delay. To this end, the method includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.

    Abstract translation: 通过硅通孔（TSV）形成的方法使用低k电介质材料作为通孔绝缘层，从而提高步骤覆盖并最小化电阻电容（RC）延迟。 为此，该方法包括在半导体衬底中形成初级通孔，在初级通孔中沉积低k电介质材料，通过在主通孔中蚀刻低k电介质形成次通孔， 同时形成低k电介质层的通孔绝缘层和金属间介电层的方式。 通孔绝缘层由侧壁上的低k电介质材料和限定初级通孔的衬底的底面形成，并且金属介电层形成在衬底的上表面上。 然后在包括在二次通孔中的基板上形成金属层，并且从半导体基板的上表面选择性地去除金属层。

    Integrated Circuit Devices Having Through-Silicon Via Structures and Methods of Manufacturing the Same
    10.
    发明申请
    Integrated Circuit Devices Having Through-Silicon Via Structures and Methods of Manufacturing the Same 有权
    具有通硅结构的集成电路器件及其制造方法

    公开(公告)号：US20170053872A1

    公开(公告)日：2017-02-23

    申请号：US15235608

    申请日：2016-08-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ho-jin Lee ,  Byung-lyul Park ,  Jin-ho An

    IPC: H01L23/538 ,  H01L21/768 ,  H01L23/00

    CPC classification number: H01L23/5384 ,  H01L21/76841 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/18161

    Abstract: Integrated circuit (IC) devices are provided including a substrate having a first sidewall defining a first through hole that is a portion of a through-silicon via (TSV) space, an interlayer insulating layer having a second sidewall and a protrusion, wherein the second sidewall defines a second through hole providing another portion of the TSV space and communicating with the first through hole, and the protrusion protrudes toward the inside of the TSV space and defines an undercut region in the first through hole, a TSV structure penetrating the substrate and the interlayer insulating layer and extending through the first through hole and the second through hole, and a via insulating layer surrounding the TSV structure in the first through hole and the second through hole.

    Abstract translation: 提供集成电路（IC）装置，其包括具有限定作为穿硅通孔（TSV）空间的一部分的第一通孔的第一侧壁的衬底，具有第二侧壁和突起的层间绝缘层，其中第二通孔 侧壁限定提供TSV空间的另一部分并与第一通孔连通的第二通孔，并且突出部朝向TSV空间的内部突出，并且在第一通孔中限定底切区域，穿透基板的TSV结构， 所述层间绝缘层延伸穿过所述第一通孔和所述第二通孔;以及通孔绝缘层，其围绕所述第一通孔和所述第二通孔中的TSV结构。

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