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    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    11.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190371808A1

    公开(公告)日：2019-12-05

    申请号：US16266409

    申请日：2019-02-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kangyoon Choi ,  Gilsung Lee ,  Dong-Sik Lee ,  Yongsik Yim ,  Eunsuk Cho

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/28

    Abstract: Provided is a three-dimensional semiconductor memory device include a first stack structure and a second stack structure adjacent to each other on a substrate, a first common source plug between the first stack structure and the second stack structure, a second common source plug between the first stack structure and the second stack structure, and a vertical dielectric structure between the first common source plug and the second common source plug. Each of the first stack structure and the second stack structure may include a plurality of insulation layers and a plurality of electrodes alternately stacked on the substrate. The first common source plug may be connected to the substrate. The second common source plug may be spaced apart from the substrate.

    Three-dimensional semiconductor memory device
    14.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11641738B2

    公开(公告)日：2023-05-02

    申请号：US17021416

    申请日：2020-09-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woosung Yang ,  Byungjin Lee ,  Bumkyu Kang ,  Dong-Sik Lee

    IPC: H01L27/11539 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/528 ,  H01L27/11543 ,  G11C16/08 ,  G11C7/18 ,  H01L27/11578

    Abstract: A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    15.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220189991A1

    公开(公告)日：2022-06-16

    申请号：US17687131

    申请日：2022-03-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byungjin LEE ,  Dong-Sik Lee ,  Joon-Sung Lim

    IPC: H01L27/11582 ,  H01L27/11565

    Abstract: A semiconductor device is provided. The semiconductor device includes a stack structure that includes a plurality of dielectric layers spaced apart from each other on a substrate, a plurality of electrodes interposed between the plurality of dielectric layers, and a plurality of stopper layers interposed between the plurality of dielectric layers; and a vertical channel structure that penetrates the stack structure. Each of the plurality of electrodes and the plurality of stopper layers is disposed in a corresponding empty space interposed between the plurality of dielectric layers, the plurality of stopper layers includes a first stopper layer and a second stopper layer that is interposed between the first stopper layer and the substrate, and at least one of the plurality of electrodes is interposed between the first stopper layer and the second stopper layer.

    Three-dimensional semiconductor memory device
    16.
    发明授权
    Three-dimensional semiconductor memory device 审中-公开

    公开(公告)号：US10672792B2

    公开(公告)日：2020-06-02

    申请号：US16266409

    申请日：2019-02-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kangyoon Choi ,  Gilsung Lee ,  Dong-Sik Lee ,  Yongsik Yim ,  Eunsuk Cho

    IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/28

    Abstract: Provided is a three-dimensional semiconductor memory device include a first stack structure and a second stack structure adjacent to each other on a substrate, a first common source plug between the first stack structure and the second stack structure, a second common source plug between the first stack structure and the second stack structure, and a vertical dielectric structure between the first common source plug and the second common source plug. Each of the first stack structure and the second stack structure may include a plurality of insulation layers and a plurality of electrodes alternately stacked on the substrate. The first common source plug may be connected to the substrate. The second common source plug may be spaced apart from the substrate.

    Three-dimensional semiconductor memory device
    17.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US10128266B2

    公开(公告)日：2018-11-13

    申请号：US15592030

    申请日：2017-05-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung Hoon Lee ,  Keejeong Rho ,  Sejun Park ,  Jinhyun Shin ,  Dong-Sik Lee ,  Woong-Seop Lee

    IPC: H01L27/11582 ,  H01L23/528 ,  G11C16/08 ,  H01L27/11556 ,  H01L27/1157

    Abstract: A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    19.
    发明公开
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240098990A1

    公开(公告)日：2024-03-21

    申请号：US18127404

    申请日：2023-03-28

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Sung-Min Hwang ,  Jaehoon Lee ,  Seunghyun Cho ,  Jae-Joo Shim ,  Dong-Sik Lee

    IPC: H01L29/76 ,  H01L23/528

    CPC classification number: H10B41/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/35

    Abstract: A semiconductor device includes a gate stack structure including insulating patterns and conductive patterns which are alternately stacked, a first separation structure penetrating the gate stack structure, a second separation structure penetrating the gate stack structure and being adjacent to the first separation structure, first and second memory channel structures penetrating the gate stack structure and disposed between the first separation structure and the second separation structure, a first bit line overlapping with the first and second memory channel structures and electrically connected to the first memory channel structure, and a second bit line overlapping with the first and second memory channel structures and the first bit line and electrically connected to the second memory channel structure.

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