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11.发明授权公开(公告)号：US10679717B2
公开(公告)日：2020-06-09
申请号：US16426391
申请日：2019-05-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eun-Ji Kim , Jung-June Park , Jeong-Don Ihm , Byung-Hoon Jeong , Young-Don Choi
Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
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12.发明申请公开(公告)号：US20180336958A1
公开(公告)日：2018-11-22
申请号：US15977553
申请日：2018-05-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eun-Ji Kim , Jung-June Park , Jeong-Don Ihm , Byung-Hoon Jeong , Young-Don Choi
CPC classification number: G11C29/025 , G11C5/063 , G11C7/1048 , G11C7/1057 , G11C7/1084 , G11C16/06 , G11C16/102 , G11C16/26 , G11C29/022 , G11C29/028
Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
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13.发明授权Semiconductor devices including protection patterns and methods of forming the same 有权包括保护模式的半导体器件及其形成方法公开(公告)号：US09293415B2
公开(公告)日：2016-03-22
申请号：US14708800
申请日：2015-05-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eun-Ji Kim , Sung-Dong Cho , Hyoung-Yol Mun , Yeong-Lyeol Park , Seung-Taek Lee
IPC: H01L23/52 , H01L23/528 , H01L23/48 , H01L23/532
CPC classification number: H01L23/528 , H01L23/481 , H01L23/53228 , H01L23/53257 , H01L23/564 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05571 , H01L2224/13025 , H01L2224/131 , H01L2224/14181 , H01L2224/16146 , H01L2224/16225 , H01L2224/16237 , H01L2924/00012 , H01L2924/014
Abstract: Semiconductor devices including a protection pattern for reducing galvanic corrosion and methods of forming the semiconductor devices are provided. The semiconductor devices may include a substrate including a keep out zone (KOZ) and a plurality of interconnections, which may be disposed outside of the KOZ on the substrate. The semiconductor devices may also include a through silicon via (TSV) in the KOZ. The TSV may pass through the substrate. The semiconductor device may further include a protection pattern, which may be electrically insulated from the TSV, may be disposed in the KOZ and may include a different conductive material from the TSV. A lower end of the protection pattern may be disposed at a level higher than a lower end of the TSV.
Abstract translation: 提供了包括用于减少电偶腐蚀的保护图案的半导体器件和形成半导体器件的方法。 半导体器件可以包括包括保留区（KOZ）和多个互连的衬底，其可以设置在衬底上的KOZ的外部。 半导体器件还可以包括KOZ中的硅通孔（TSV）。 TSV可以通过衬底。 半导体器件还可以包括可以与TSV电绝缘的保护图案，可以设置在KOZ中，并且可以包括与TSV不同的导电材料。 保护图案的下端可以设置在高于TSV的下端的水平。
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公开(公告)号：US20230292521A1
公开(公告)日：2023-09-14
申请号：US18153763
申请日：2023-01-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Woo Yong JEON , Eun-Ji Kim , Ji Young Kim , Moo Rym Choi
IPC: H10B43/40 , H10B43/10 , H10B43/27 , H10B43/35 , H01L23/522 , H01L23/528 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40
CPC classification number: H10B43/40 , H10B43/10 , H10B43/27 , H10B43/35 , H01L23/5226 , H01L23/5283 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40
Abstract: A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit and a first bonding pad, the first bonding pad connected to the peripheral circuit, a cell structure on the peripheral circuit structure, the cell structure including a second bonding pad bonded to the first bonding pad, and a pad structure on the cell structure. The cell structure includes a cell substrate having a first face, a second face opposite to the first face, a first contact plug extending through the cell substrate and connected to an electrode layer, and a second contact plug extending through the cell substrate and connected to the cell substrate. Each of the first contact plug and the second contact plug is connected to the pad structure, and a bypass via is in contact with the pad structure on the second face.
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15.发明授权公开(公告)号：US11742040B2
公开(公告)日：2023-08-29
申请号：US17704345
申请日：2022-03-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eun-Ji Kim , Jung-June Park , Jeong-Don Ihm , Byung-Hoon Jeong , Young-Don Choi
CPC classification number: G11C29/025 , G11C5/063 , G11C7/1048 , G11C7/1057 , G11C7/1084 , G11C16/06 , G11C16/102 , G11C16/26 , G11C29/022 , G11C29/028
Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
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Patent Agency Ranking
公开(公告)号：US20180131478A1
公开(公告)日：2018-05-10
申请号：US15807240
申请日：2017-11-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seong-Jun SONG , Kyung-Hwan Jo , Eun-Ji Kim , Jae-Hyun Kwon , Sungjin Kim , Donginn Seo , Dohyeon Lee , Seung Chul Lee
CPC classification number: H04L5/001 , H04B1/0064 , H04B7/04 , H04B7/0848 , H04B17/13 , H04W40/02
Abstract: An electronic device is provided. The electronic device includes a first antenna for a first band and a second band, a second antenna for the second band and a third band and a pre-processing unit configured to generate, based on identifying a frequency band of a first signal received via the first antenna and a frequency band of a second signal received via the second antenna are the second band, a pre-processed signal by combining the first signal and the second signal based on a ratio of a weight factor, and to transmit the pre-processed signal to a first radio frequency (RF) receiver.
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17.发明授权Integrated circuit devices including through-silicon via (TSV) contact pads electronically insulated from a substrate 有权集成电路器件包括与衬底电绝缘的穿硅通孔（TSV）接触焊盘公开(公告)号：US08890282B2
公开(公告)日：2014-11-18
申请号：US14013086
申请日：2013-08-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Woon-Seob Lee , Sin-Woo Kang , Ki-Young Yun , Sung-Dong Cho , Eun-Ji Kim , Yeong-Lyeol Park
CPC classification number: H01L23/481 , H01L23/585 , H01L24/05 , H01L24/16 , H01L24/48 , H01L25/0657 , H01L2224/0401 , H01L2224/05556 , H01L2224/16145 , H01L2224/48091 , H01L2224/48145 , H01L2924/00014 , H01L2224/13099 , H01L2224/45099 , H01L2924/00012
Abstract: An integrated circuit device includes a substrate having a plurality of device patterns thereon. A device isolation layer is provided on the substrate, an interlayer dielectric layer is provided on the device isolation layer and the substrate, and a conductive via extends through the interlayer dielectric layer and the device isolation layer and into the substrate. A conductive via contact pad is provided on the interlayer dielectric layer in electrical contact with the conductive via. In plan view, the conductive via contact pad is confined within an area of the interlayer dielectric layer and/or an area of the device isolation layer that electrically insulates the conductive via contact pad from the substrate. Related methods and devices are also discussed.
Abstract translation: 集成电路器件包括其上具有多个器件图案的衬底。 在衬底上设置器件隔离层，在器件隔离层和衬底上提供层间介质层，并且导电通孔延伸穿过层间介质层和器件隔离层并进入衬底。 导电通孔接触焊盘设置在与导电通孔电接触的层间电介质层上。 在平面图中，导电通孔接触焊盘被限制在层间介质层的区域和/或器件隔离层的使导电通孔接触焊盘与衬底电绝缘的区域中。 还讨论了相关的方法和设备。
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18.发明申请Integrated Circuit Devices Including Through-Silicon Via (TSV) Contact Pads Electronically Insulated from a Substrate 有权集成电路器件包括从基板电子绝缘的硅通孔（TSV）接触垫公开(公告)号：US20140124951A1
公开(公告)日：2014-05-08
申请号：US14013086
申请日：2013-08-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Woon-Seob Lee , Sin-Woo Kang , Ki-Young Yun , Sung-Dong Cho , Eun-Ji Kim , Yeong-Lyeol Park
IPC: H01L23/48
CPC classification number: H01L23/481 , H01L23/585 , H01L24/05 , H01L24/16 , H01L24/48 , H01L25/0657 , H01L2224/0401 , H01L2224/05556 , H01L2224/16145 , H01L2224/48091 , H01L2224/48145 , H01L2924/00014 , H01L2224/13099 , H01L2224/45099 , H01L2924/00012
Abstract: An integrated circuit device includes a substrate having a plurality of device patterns thereon. A device isolation layer is provided on the substrate, an interlayer dielectric layer is provided on the device isolation layer and the substrate, and a conductive via extends through the interlayer dielectric layer and the device isolation layer and into the substrate. A conductive via contact pad is provided on the interlayer dielectric layer in electrical contact with the conductive via. In plan view, the conductive via contact pad is confined within an area of the interlayer dielectric layer and/or an area of the device isolation layer that electrically insulates the conductive via contact pad from the substrate. Related methods and devices are also discussed.
Abstract translation: 集成电路器件包括其上具有多个器件图案的衬底。 在衬底上设置器件隔离层，在器件隔离层和衬底上提供层间介质层，并且导电通孔延伸穿过层间介质层和器件隔离层并进入衬底。 导电通孔接触焊盘设置在与导电通孔电接触的层间电介质层上。 在平面图中，导电通孔接触焊盘被限制在层间介质层的区域和/或器件隔离层的使导电通孔接触焊盘与衬底电绝缘的区域中。 还讨论了相关的方法和设备。
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19.发明授权公开(公告)号：US12073898B2
公开(公告)日：2024-08-27
申请号：US18361132
申请日：2023-07-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eun-Ji Kim , Jung-June Park , Jeong-Don Ihm , Byung-Hoon Jeong , Young-Don Choi
CPC classification number: G11C29/025 , G11C5/063 , G11C7/1048 , G11C7/1057 , G11C7/1084 , G11C16/06 , G11C16/102 , G11C16/26 , G11C29/022 , G11C29/028
Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
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公开(公告)号：US11410951B2
公开(公告)日：2022-08-09
申请号：US17207242
申请日：2021-03-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyungeun Choi , Eun-Ji Kim , Jong-Ho Moon , Hyoungyol Mun , Han-Sik Yoo , Kiseok Lee , Seungjae Jung , Taehyun An , Sangyeon Han , Yoosang Hwang
IPC: H01L27/108 , G11C11/408 , H01L25/065 , G11C11/4091 , H01L23/00 , H01L25/18
Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.
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