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公开(公告)号:US20240234325A1
公开(公告)日:2024-07-11
申请号:US18239846
申请日:2023-08-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: JOONGHYUN BAEK , HYUNSOO CHUNG , SEOK-HONG KWON
IPC: H01L23/538 , H01L23/00 , H01L23/498 , H01L25/065 , H01L25/10
CPC classification number: H01L23/5383 , H01L23/49811 , H01L23/562 , H01L25/0655 , H01L25/105 , H01L24/16 , H01L2224/16227
Abstract: A semiconductor package includes a first redistribution layer, a first semiconductor chip, and a second semiconductor chip. The first redistribution layer includes a first intervening interconnection layer and a first upper interconnection layer. The first intervening interconnection layer includes a first intervening insulating layer, a first intervening redistribution pattern, and a stress buffer pattern, which is spaced apart from the first intervening redistribution pattern and is in an electrically floated state. The first upper interconnection layer includes a first upper insulating layer, a first upper redistribution pattern, and a first test pad on the first upper redistribution pattern. An area of the stress buffer pattern is larger than an area of the first test pad.
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公开(公告)号:US20220216190A1
公开(公告)日:2022-07-07
申请号:US17370594
申请日:2021-07-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: HYUNSOO CHUNG , TAEWON YOO , MYUNGKEE CHUNG , JINCHAN AHN
IPC: H01L25/10 , H01L23/00 , H01L23/498
Abstract: Disclosed is a semiconductor package comprising a semiconductor chip and a redistribution layer. The semiconductor chip includes a semiconductor substrate, a passivation layer, and first power, second power, and signal pads exposed from the passivation layer. The redistribution layer includes a photosensitive dielectric layer, and first to third redistribution patterns and a high-k dielectric pattern that are in the photosensitive dielectric layer. The first, second, and third redistribution patterns are respectively connected to the first power, second power, and signal pads. The high-k dielectric pattern is between the first and second redistribution patterns. The photosensitive dielectric layer includes a first dielectric material. The high-k dielectric pattern includes a second dielectric material whose dielectric constant greater than that of the first dielectric material. The high-k dielectric pattern is in contact with the passivation layer. The passivation layer includes a dielectric material different from the first and second dielectric materials.
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公开(公告)号:US20150102505A1
公开(公告)日:2015-04-16
申请号:US14326631
申请日:2014-07-09
Applicant: SAMSUNG ELECTRONICS CO., LTD
Inventor: HYUNSOO CHUNG , SEUNGDUK BAEK , IN-YOUNG LEE , TAE-JE CHO
IPC: H01L25/00 , H01L23/48 , H01L21/56 , H01L25/065 , H01L23/00
CPC classification number: H01L25/50 , H01L21/563 , H01L23/295 , H01L23/3128 , H01L23/3135 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/131 , H01L2224/16146 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/81005 , H01L2224/81815 , H01L2224/83191 , H01L2224/83192 , H01L2224/92125 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/15311 , H01L2924/181 , H01L2224/81 , H01L2924/014 , H01L2224/83 , H01L2924/00
Abstract: A semiconductor package and a method of fabricating the same. The method may include mounting a lower stack including a plurality of lower semiconductor chips on a substrate and mounting an upper stack including a plurality of upper semiconductor chips on the lower stack. According to example embodiments of the inventive concept, the semiconductor package can be easily fabricated.
Abstract translation: 一种半导体封装及其制造方法。 该方法可以包括将包括多个下半导体芯片的下堆叠安装在基板上,并且在下堆叠上安装包括多个上半导体芯片的上堆叠。 根据本发明构思的示例实施例,可以容易地制造半导体封装。
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公开(公告)号:US20250096214A1
公开(公告)日:2025-03-20
申请号:US18626691
申请日:2024-04-04
Applicant: Samsung Electronics Co., Ltd.
Inventor: HYUNSOO CHUNG , YOUNG LYONG KIM , CHI WOO LEE
Abstract: An embodiment provides a semiconductor package including: a redistribution structure; an interconnection structure on the redistribution structure; a memory stacking structure disposed on the redistribution structure and including a buffer die and core dies stacked on the buffer die; a semiconductor die disposed on the buffer die and on the interconnection structure; and an optical engine disposed on the interconnection structure.
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公开(公告)号:US20240006356A1
公开(公告)日:2024-01-04
申请号:US18181731
申请日:2023-03-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: INHYO HWANG , YOUNG LYONG KIM , HYUNSOO CHUNG
CPC classification number: H01L24/06 , H01L22/32 , H01L23/562 , H01L23/564 , H01L23/585 , H01L24/08 , H01L2924/35121 , H01L21/78 , H01L22/12 , H01L2224/06517 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511 , H10B80/00
Abstract: A semiconductor device may include a first substrate including device and edge regions, a first insulating structure on the first substrate, first metal pads and first dummy pads at the uppermost end of the first insulating structure, a second insulating structure on the first insulating structure, second metal pads and second dummy pads at the lowermost end of the second insulating structure, a first interconnection structure in the first insulating structure, electrically connected to the first metal pads and electrically isolated from the first dummy pads, and a second interconnection structure in the second insulating structure, electrically connected to the second metal pads, and electrically isolated from the second dummy pads. Ones of the first metal pads may be in contact with respective ones of the second metal pads on the device region, and ones of the first dummy pads may be in contact with respective ones of the second dummy pads on the edge region.
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公开(公告)号:US20230111207A1
公开(公告)日:2023-04-13
申请号:US17850488
申请日:2022-06-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: HYUNSOO CHUNG , DAEWOO KIM , YOUNGLYONG KIM
Abstract: A semiconductor package includes; a redistribution wiring layer, a controller chip centrally disposed on the redistribution wiring layer, a first sealant disposed on the redistribution wiring layer, wherein the controller chip is buried in the first sealant, through vias connected to the redistribution wiring layer through the first sealant, and a sub-package disposed on an upper surface of the first sealant. The sub-package may include a first stack structure disposed to one side of the controller chip on the upper surface of the first sealant and including vertically stacked chips, a second stack structure disposed to another side of the controller chip on the upper surface of the first sealant adjacent to the first stack structure in a first horizontal direction and including vertically stacked chips, and a second sealant sealing the first stack structure and the second stack structure.
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公开(公告)号:US20220037295A1
公开(公告)日:2022-02-03
申请号:US17205659
申请日:2021-03-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: HYUNSOO CHUNG , TAEWON YOO , MYUNGKEE CHUNG
Abstract: A semiconductor package includes a bottom package and an upper redistribution layer disposed on the bottom package. The bottom package includes a substrate and a semiconductor chip disposed on the substrate. A conductive pillar extends upwardly from the substrate and is spaced apart from the semiconductor chip. A mold layer is disposed on the substrate and encloses the semiconductor chip and lateral side surfaces of the conductive pillar. The conductive pillar includes a connection pillar configured to electrically connect the substrate to the upper redistribution layer and an alignment pillar that is spaced apart from the connection pillar. The upper redistribution layer includes a redistribution metal pattern configured to be electrically connected to the connection pillar. A first insulating layer is in direct contact with a top surface of the redistribution metal pattern. A top surface of the alignment pillar is in direct contact with the first insulating layer.
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公开(公告)号:US20210167007A1
公开(公告)日:2021-06-03
申请号:US16931129
申请日:2020-07-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: HYUNSOO CHUNG , TAEWON YOO , MYUNGKEE CHUNG
IPC: H01L23/528 , H01L23/532 , H01L23/522 , H01L23/00
Abstract: A semiconductor package includes an electrode pad arranged in a first direction parallel to an upper surface of a semiconductor chip, a first protective layer at least partially surrounding an edge of the electrode pad and having a first opening that is above the electrode pad, a second protective layer at least partially surrounding the first protective layer and having a second opening that is above the electrode pad, and a redistribution structure electrically connected to the electrode pad and covering at least a part of an upper surface of the second protective layer. A first width of the first opening in the first direction is equal to or greater than a maximum width of the redistribution structure in the first direction, and a second width of the second opening in the first direction is less than the maximum width of the redistribution structure in the first direction.
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公开(公告)号:US20170162500A1
公开(公告)日:2017-06-08
申请号:US15259024
申请日:2016-09-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Chanho LEE , HYUNSOO CHUNG , Myeong Soon PARK
IPC: H01L23/522 , H01L23/00 , H01L23/498
CPC classification number: H01L23/5223 , H01L23/49816 , H01L24/13 , H01L24/14 , H01L2224/0401 , H01L2224/05567 , H01L2224/13021 , H01L2224/13022 , H01L2224/13082 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/1403 , H01L2224/14104 , H01L2224/14166 , H01L2224/16238 , H01L2924/014 , H01L2924/00014
Abstract: A semiconductor device comprising: a substrate; a decoupling capacitor disposed on the substrate; a first connection pad vertically overlapping with the decoupling capacitor; a passivation layer exposing a portion of the first connection pad; and a first solder bump disposed on the first connection pad and covering a portion of a top surface of the passivation layer.
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