SEMICONDUCTOR PACKAGE
    11.
    发明公开

    公开(公告)号:US20240234325A1

    公开(公告)日:2024-07-11

    申请号:US18239846

    申请日:2023-08-30

    Abstract: A semiconductor package includes a first redistribution layer, a first semiconductor chip, and a second semiconductor chip. The first redistribution layer includes a first intervening interconnection layer and a first upper interconnection layer. The first intervening interconnection layer includes a first intervening insulating layer, a first intervening redistribution pattern, and a stress buffer pattern, which is spaced apart from the first intervening redistribution pattern and is in an electrically floated state. The first upper interconnection layer includes a first upper insulating layer, a first upper redistribution pattern, and a first test pad on the first upper redistribution pattern. An area of the stress buffer pattern is larger than an area of the first test pad.

    SEMICONDUCTOR PACKAGE
    12.
    发明申请

    公开(公告)号:US20220216190A1

    公开(公告)日:2022-07-07

    申请号:US17370594

    申请日:2021-07-08

    Abstract: Disclosed is a semiconductor package comprising a semiconductor chip and a redistribution layer. The semiconductor chip includes a semiconductor substrate, a passivation layer, and first power, second power, and signal pads exposed from the passivation layer. The redistribution layer includes a photosensitive dielectric layer, and first to third redistribution patterns and a high-k dielectric pattern that are in the photosensitive dielectric layer. The first, second, and third redistribution patterns are respectively connected to the first power, second power, and signal pads. The high-k dielectric pattern is between the first and second redistribution patterns. The photosensitive dielectric layer includes a first dielectric material. The high-k dielectric pattern includes a second dielectric material whose dielectric constant greater than that of the first dielectric material. The high-k dielectric pattern is in contact with the passivation layer. The passivation layer includes a dielectric material different from the first and second dielectric materials.

    SEMICONDUCTOR PACKAGE INCLUDING SUB-PACKAGE

    公开(公告)号:US20230111207A1

    公开(公告)日:2023-04-13

    申请号:US17850488

    申请日:2022-06-27

    Abstract: A semiconductor package includes; a redistribution wiring layer, a controller chip centrally disposed on the redistribution wiring layer, a first sealant disposed on the redistribution wiring layer, wherein the controller chip is buried in the first sealant, through vias connected to the redistribution wiring layer through the first sealant, and a sub-package disposed on an upper surface of the first sealant. The sub-package may include a first stack structure disposed to one side of the controller chip on the upper surface of the first sealant and including vertically stacked chips, a second stack structure disposed to another side of the controller chip on the upper surface of the first sealant adjacent to the first stack structure in a first horizontal direction and including vertically stacked chips, and a second sealant sealing the first stack structure and the second stack structure.

    SEMICONDUCTOR PACKAGE
    17.
    发明申请

    公开(公告)号:US20220037295A1

    公开(公告)日:2022-02-03

    申请号:US17205659

    申请日:2021-03-18

    Abstract: A semiconductor package includes a bottom package and an upper redistribution layer disposed on the bottom package. The bottom package includes a substrate and a semiconductor chip disposed on the substrate. A conductive pillar extends upwardly from the substrate and is spaced apart from the semiconductor chip. A mold layer is disposed on the substrate and encloses the semiconductor chip and lateral side surfaces of the conductive pillar. The conductive pillar includes a connection pillar configured to electrically connect the substrate to the upper redistribution layer and an alignment pillar that is spaced apart from the connection pillar. The upper redistribution layer includes a redistribution metal pattern configured to be electrically connected to the connection pillar. A first insulating layer is in direct contact with a top surface of the redistribution metal pattern. A top surface of the alignment pillar is in direct contact with the first insulating layer.

    REDISTRIBUTION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

    公开(公告)号:US20210167007A1

    公开(公告)日:2021-06-03

    申请号:US16931129

    申请日:2020-07-16

    Abstract: A semiconductor package includes an electrode pad arranged in a first direction parallel to an upper surface of a semiconductor chip, a first protective layer at least partially surrounding an edge of the electrode pad and having a first opening that is above the electrode pad, a second protective layer at least partially surrounding the first protective layer and having a second opening that is above the electrode pad, and a redistribution structure electrically connected to the electrode pad and covering at least a part of an upper surface of the second protective layer. A first width of the first opening in the first direction is equal to or greater than a maximum width of the redistribution structure in the first direction, and a second width of the second opening in the first direction is less than the maximum width of the redistribution structure in the first direction.

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