公开(公告)号：US11804427B2

公开(公告)日：2023-10-31

申请号：US17177305

申请日：2021-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Seokhyun Lee ,  Kyoung Lim Suk ,  Jaegwon Jang ,  Gwangjae Jeon

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/32225

Abstract: A semiconductor package may include a redistribution substrate, a connection terminal, and a semiconductor chip sequentially stacked. The redistribution substrate may include an insulating layer, a plurality of redistribution patterns, which are vertically stacked in the insulating layer, and each of which includes interconnection and via portions, and a bonding pad on the interconnection portion of the topmost redistribution pattern. The topmost redistribution pattern and the bonding pad may include different metallic materials. The bonding pad may have first and second surfaces opposite to each other. The first surface of the bonding pad may be in contact with a top surface of the interconnection portion of the topmost redistribution pattern. A portion of the second surface of the bonding pad may be in contact with the connection terminal. The insulating layer may be extended to be in contact with the remaining portion of the second surface.

公开(公告)号：US11145611B2

公开(公告)日：2021-10-12

申请号：US16795795

申请日：2020-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Jungho Park ,  Seokhyun Lee ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a semiconductor chip provided on a first surface of the redistribution insulation layer and electrically connected to the redistribution pattern, and a lower electrode pad provided on a second surface opposite to the first surface of the redistribution insulating layer, the lower electrode pad including a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad.

公开(公告)号：US09818703B2

公开(公告)日：2017-11-14

申请号：US15293786

申请日：2016-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegwon Jang ,  Youngjae Kim ,  Baikwoo Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3121 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15151 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A printed circuit board includes chip regions on which semiconductor chips are mounted, and a scribe region surrounding each of the chip regions. The scribe region includes first vent holes that are configured to receive a flow of molding resin and are arranged along a first direction corresponding to a flow direction of the molding resin.

公开(公告)号：US11955499B2

公开(公告)日：2024-04-09

申请号：US17363931

申请日：2021-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjung Kim ,  Dongkyu Kim ,  Kyounglim Suk ,  Jaegwon Jang ,  Hyeonjeong Hwang

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14636 ,  H01L27/14618 ,  H01L27/14634 ,  H01L24/16 ,  H01L27/14621 ,  H01L27/14625 ,  H01L2224/16227

Abstract: An image sensor package includes a glass substrate configured to focus incident light, a first redistribution layer and a second redistribution layer both disposed under the glass substrate while being horizontally spaced apart from each other by a first distance, an image sensor disposed such that an upper surface thereof is vertically spaced apart from both a lower surface of the first redistribution layer and a lower surface of the second redistribution layer by a second distance, and a first connector that connects both the first redistribution layer and the second redistribution layer to the image sensor. The thickness of the glass substrate is 0.6 to 0.8 mm. The first distance is smaller than the horizontal length of the image sensor by 50 μm to 1 mm. The second distance is equal to or less than 0.1 mm.

公开(公告)号：US11869775B2

公开(公告)日：2024-01-09

申请号：US18169161

申请日：2023-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Kyoung Lim Suk ,  Ae-Nee Jang ,  Jaegwon Jang

IPC: H01L21/56 ,  H01L23/485 ,  H01L23/498 ,  H01L21/60 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L23/485 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/73 ,  H01L21/60 ,  H01L2224/023 ,  H01L2224/0508 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/13024 ,  H01L2224/73204 ,  H01L2924/15311

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.

公开(公告)号：US20230197469A1

公开(公告)日：2023-06-22

申请号：US18169161

申请日：2023-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Kyoung Lim Suk ,  Ae-Nee Jang ,  Jaegwon Jang

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/485 ,  H01L21/60

CPC classification number: H01L21/563 ,  H01L24/73 ,  H01L24/13 ,  H01L24/05 ,  H01L23/49816 ,  H01L23/485 ,  H01L2224/05548 ,  H01L2224/05022 ,  H01L2924/15311 ,  H01L21/60 ,  H01L2224/13024 ,  H01L2224/0508 ,  H01L2224/73204 ,  H01L2224/023

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.

公开(公告)号：US11637081B2

公开(公告)日：2023-04-25

申请号：US17474614

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Jungho Park ,  Seokhyun Lee ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/768 ,  H01L25/065

Abstract: A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a semiconductor chip provided on a first surface of the redistribution insulation layer and electrically connected to the redistribution pattern, and a lower electrode pad provided on a second surface opposite to the first surface of the redistribution insulating layer, the lower electrode pad including a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad.

公开(公告)号：US20230085930A1

公开(公告)日：2023-03-23

申请号：US18060853

申请日：2022-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonjeong HWANG ,  Kyoung Lim Suk ,  Seokhyun Lee ,  Jaegwon Jang

IPC: H01L25/10 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00 ,  H01L23/31

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a first molding layer on the first redistribution substrate and covering a top surface and lateral surfaces of the first semiconductor chip, a second redistribution substrate on the first molding layer, and an adhesive film between the second redistribution substrate and the first molding layer. The adhesive film is spaced apart from the first semiconductor chip and covers a top surface of the first molding layer. A lateral surface of the adhesive film is coplanar with a lateral surface of the second redistribution substrate.

公开(公告)号：US11569157B2

公开(公告)日：2023-01-31

申请号：US16946209

申请日：2020-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonho Jang ,  Jongyoun Kim ,  Jungho Park ,  Jaegwon Jang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor chip; a redistribution insulating layer including a first opening; an external connection bump including a first part in the first opening; a lower bump pad including a first surface in physical contact with the first part of the external connection bump and a second surface opposite to the first surface, wherein the first surface and the redistribution insulating layer partially overlap; and a redistribution pattern that electrically connects the lower bump pad to the semiconductor chip.

公开(公告)号：US11094636B2

公开(公告)日：2021-08-17

申请号：US16671625

申请日：2019-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegwon Jang ,  Inwon O ,  Jongyoun Kim ,  Seokhyun Lee ,  Yeonho Jang

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/528 ,  H01L23/522 ,  H01L23/66 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes a mold substrate, at least one semiconductor chip disposed in the mold substrate and including chip pads, and a redistribution wiring layer covering a first surface of the mold substrate and including a first redistribution wiring and a second redistribution wiring stacked in at least two levels to be electrically connected to the chip pads. The first redistribution wiring includes a signal line extending in a first region, and the second redistribution wiring includes a ground line in a second region overlapping with the first region. The ground line has a plurality of through holes of polygonal column shapes.