公开(公告)号：US20230275021A1

公开(公告)日：2023-08-31

申请号：US17738393

申请日：2022-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  Jeonghyuk Yim ,  Inchan Hwang ,  Gilhwan Son ,  Seungyoung Lee ,  Saehan Park ,  Janggeun Lee ,  Myunghoon Jung ,  Seungchan Yun ,  Buhyun Ham ,  Kang-ILL Seo

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/302 ,  H01L21/8234

CPC classification number: H01L23/5286 ,  H01L23/5283 ,  H01L23/5226 ,  H01L21/302 ,  H01L21/823475

Abstract: Integrated circuit devices may include a transistor, a passive device, a substrate extending between the transistor and the passive device and a power rail. The passive device may be spaced apart from the substrate. Each of the passive device and the power rail may have a first surface facing the substrate, and the first surface of the passive device is closer than the first surface of the power rail to the substrate.

公开(公告)号：US20220367658A1

公开(公告)日：2022-11-17

申请号：US17504720

申请日：2021-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghyuk Yim ,  Byounghak Hong ,  Jungsu Kim ,  Kang-ill Seo

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

公开(公告)号：US10811505B2

公开(公告)日：2020-10-20

申请号：US15990983

申请日：2018-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghan Lee ,  Wandon Kim ,  Jaeyeol Song ,  Jeonghyuk Yim ,  HyungSuk Jung

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/768

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.

公开(公告)号：US20250063765A1

公开(公告)日：2025-02-20

申请号：US18938867

申请日：2024-11-06

Applicant: Samsung Electronics Co, Ltd.

Inventor： Jeonghyuk Yim ,  Byounghak Hong ,  Jungsu Kim ,  Kang-ill Seo

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

公开(公告)号：US12170322B2

公开(公告)日：2024-12-17

申请号：US17504720

申请日：2021-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghyuk Yim ,  Byounghak Hong ,  Jungsu Kim ,  Kang-ill Seo

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

公开(公告)号：US12142564B2

公开(公告)日：2024-11-12

申请号：US18457000

申请日：2023-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saehan Park ,  Hoonseok Seo ,  Jeonghyuk Yim ,  Ki-Il Kim ,  Gil Hwan Son

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/822 ,  H01L23/00 ,  H01L23/48 ,  H01L27/06

Abstract: Provided is a semiconductor architecture including a carrier substrate, a landing pad included in the carrier substrate, a first semiconductor device provided on a first surface of the carrier substrate, the first semiconductor device including a first component provided on the landing pad, and a second semiconductor device provided on a second surface of the carrier substrate, a second component protruding from the second semiconductor device being provided on the landing pad.

公开(公告)号：US20240222451A1

公开(公告)日：2024-07-04

申请号：US18243818

申请日：2023-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wandon Kim ,  Jaeseoung Park ,  Hyunwoo Kim ,  Hyunbae Lee ,  Jeonghyuk Yim ,  Hyoseok Choi

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active region extending in a first direction, a gate structure extending in a second direction, a source/drain region on the active region, a first contact structure connected to the source/drain region, and a second contact structure connected to the first contact structure. The second contact structure includes a first layer including a first grain and a second layer including second grains on the first layer. Within the first layer, a maximum vertical distance between a lowermost end of the first grain and an uppermost end of the first grain is equal to a vertical distance between a lowermost end of the first layer and an uppermost end of the first layer. A size of the first grain is greater than a size of each of the second grains. A width of the first layer is greater than a width of the first contact structure.

公开(公告)号：US11901240B2

公开(公告)日：2024-02-13

申请号：US17223803

申请日：2021-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyuk Yim ,  Kang Ill Seo

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/823487 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827

Abstract: Provided is a vertical field-effect transistor (VFET) device which includes: a substrate; a plurality of single-fin VFETs including respective 1st fin structures on the substrate; and a plurality of multi-fin VFETs each of which includes a plurality of 2nd fin structures on the substrate, wherein a fin pitch of the 2nd fin structures is smaller than a fin pitch of the 1st fin structures.

公开(公告)号：US11557656B2

公开(公告)日：2023-01-17

申请号：US17024813

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghan Lee ,  Wandon Kim ,  Jaeyeol Song ,  Jeonghyuk Yim ,  HyungSuk Jung

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/768

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.

公开(公告)号：US20220157723A1

公开(公告)日：2022-05-19

申请号：US17159972

申请日：2021-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saehan Park ,  Hoonseok Seo ,  Jeonghyuk Yim ,  Ki-il Kim ,  Gil Hwan Son

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L21/822

Abstract: Provided is a semiconductor architecture including a carrier substrate, a landing pad included in the carrier substrate, a first semiconductor device provided on a first surface of the carrier substrate, the first semiconductor device including a first component provided on the landing pad, and a second semiconductor device provided on a second surface of the carrier substrate, a second component protruding from the second semiconductor device being provided on the landing pad.