公开(公告)号：US20230006040A1

公开(公告)日：2023-01-05

申请号：US17577088

申请日：2022-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmoon LEE ,  Jinbum KIM ,  Hyojin KIM ,  Yongjun NAM ,  Sujin JUNG

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/423

Abstract: An integrated circuit (IC) device includes a fin-type active region extending on a substrate in a first lateral direction. A gate line extends on the fin-type active region in a second lateral direction. The second lateral direction intersects the first lateral direction. A channel region is between the substrate and the gate line. A source/drain region is adjacent to the gate line on the fin-type active region and has a sidewall facing the channel region. A superlattice barrier is between the substrate and the channel region. The superlattice barrier is in contact with the source/drain region. The superlattice barrier has a structure in which a plurality of first sub-layers including a semiconductor layer doped with oxygen atoms and a plurality of second sub-layers including an undoped semiconductor layer are alternately stacked.

公开(公告)号：US20220005946A1

公开(公告)日：2022-01-06

申请号：US17192301

申请日：2021-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun KIM ,  Dahye KIM ,  Jinbum KIM ,  Gyeom KIM ,  Dohee KIM ,  Dongwoo KIM ,  Seunghun LEE

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

公开(公告)号：US20150214370A1

公开(公告)日：2015-07-30

申请号：US14491117

申请日：2014-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum KIM ,  Bonyoung KOO ,  Seokhoon KIM ,  Chul KIM ,  Kwan Heum LEE ,  Byeongchan LEE ,  Sujin JUNG

IPC: H01L29/78 ,  H01L29/08

CPC classification number: H01L29/0847 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a substrate provided with an active pattern; a gate structure provided on the active pattern to cross the active pattern; and source/drain regions provided at both sides of the gate structure. The active pattern includes a first region below the gate structure and second regions at both sides of the gate structure. A top surface of each of the second regions is lower than that of the first region. The source/drain regions are provided on the second regions, respectively, and each of the source/drain regions covers partially both sidewalls of each of the second regions.

Abstract translation: 半导体器件包括具有活性图案的衬底; 栅极结构，设置在所述有源图案上以穿过所述有源图案; 以及设置在栅极结构的两侧的源极/漏极区域。 有源图案包括栅极结构下方的第一区域和栅极结构两侧的第二区域。 每个第二区域的顶表面低于第一区域的顶表面。 源极/漏极区域分别设置在第二区域上，并且每个源极/漏极区域部分地覆盖每个第二区域的两个侧壁。

公开(公告)号：US20250040245A1

公开(公告)日：2025-01-30

申请号：US18602827

申请日：2024-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suk YANG ,  Sung-Hwan JANG ,  Jinbum KIM ,  Sunguk JANG

IPC: H01L27/118

Abstract: A semiconductor device includes a substrate, a first device region on the substrate, a second device region on the substrate and spaced apart from the first device region in a first direction, a first dummy region between the first device region and the second device region, and an insulating pattern in the first device region, the second device region and the first dummy region, where the first dummy region includes a seed pattern on the insulating pattern, and a seed mask pattern at least partially covering a top surface of the seed pattern and extending from the top surface of the seed pattern along a first sidewall of the seed pattern, where the insulating pattern in the first dummy region is on the substrate, and where the seed pattern includes a transition metal dichalcogenide.

公开(公告)号：US20250016993A1

公开(公告)日：2025-01-09

申请号：US18428207

申请日：2024-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Hwan JANG ,  Guifu YANG ,  Jinbum KIM ,  Sunguk JANG

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate including a recess region; a bit line contact in the recess region; a bit line on the bit line contact, the bit line extending in a first direction; a first insulating pattern covering side surfaces of the bit line contact and an inner surface of the recess region; and a second insulating pattern on the first insulating pattern, wherein an oxygen density of the first insulating pattern is higher than an oxygen density of the second insulating pattern.

公开(公告)号：US20240413246A1

公开(公告)日：2024-12-12

申请号：US18809745

申请日：2024-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun KIM ,  Dahye KIM ,  Jinbum KIM ,  Gyeom KIM ,  Dohee KIM ,  Dongwoo KIM ,  Seunghun LEE

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/04 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

公开(公告)号：US20240332186A1

公开(公告)日：2024-10-03

申请号：US18609065

申请日：2024-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum KIM

IPC: H01L23/528 ,  H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L29/0673 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate having opposite first and second surfaces, a fin-type active pattern on the first surface of the substrate, a gate structure intersecting the fin-type active pattern, a source/drain region on the fin-type active pattern at a side of the gate structure, a contact structure connected to the source/drain region, a buried conductive structure electrically connected to the contact structure and extending in a direction perpendicular to the first surface, and a conductive through structure extending from the second surface of the substrate toward the first surface of the substrate and contacting with the buried conductive structure, the conductive through structure has a first width at a level adjacent to the first surface, narrower than a second width at a level adjacent to the second surface.

公开(公告)号：US20240304666A1

公开(公告)日：2024-09-12

申请号：US18667417

申请日：2024-05-17

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Jinbum KIM ,  Gyeom KIM ,  Hyojin KIM ,  Haejun YU ,  Seunghun LEE ,  Kyungin CHOI

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L29/0653 ,  H01L29/6656 ,  H01L29/78618 ,  H01L29/78696

Abstract: An integrated circuit device is provided and includes: a fin-type active region extending in a first horizontal direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer covering a sidewall of the gate line, a source/drain region connected to the channel region on the fin-type active region and including a first portion facing the sidewall of the gate line with the insulating spacer therebetween, an air gap between the insulating spacer and the first portion of the source/drain region, and an insulating liner including a portion in contact with the source/drain region and a portion defining a size of the air gap. A method of manufacturing the integrated circuit device is further provided.

公开(公告)号：US20240282830A1

公开(公告)日：2024-08-22

申请号：US18535421

申请日：2023-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom KIM ,  Jinbum KIM ,  Sangmoon LEE

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/4175 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate insulating layer; a gate structure extending in one direction on the substrate insulating layer; a source/drain region outside of the gate structure; and a backside contact plug below the source/drain region to have a second central axis offset from a first central axis of the source/drain region in a horizontal direction, and connected to the source/drain region, wherein the source/drain region includes a first epitaxial layer including a non-silicon element in a first concentration, and a second epitaxial layer on the first epitaxial layer and including a non-silicon element in a second concentration, higher than the first concentration, and at least a portion of an upper surface of the backside contact plug is in contact with the second epitaxial layer.

公开(公告)号：US20230051597A1

公开(公告)日：2023-02-16

申请号：US17579919

申请日：2022-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil LEE ,  Youngjun KIM ,  Jinbum KIM

IPC: H01L27/108

Abstract: A semiconductor device including an active pattern; a gate structure connected to the active pattern; a bit line structure connected to the active pattern; a buried contact connected to the active pattern; a contact pattern covering the buried contact; a landing pad connected to the contact pattern; and a capacitor structure connected to the landing pad, wherein the buried contact includes a first growth portion and a second growth portion spaced apart from each other, and the landing pad includes an interposition portion between the first growth portion and the second growth portion.