-
11.发明授权公开(公告)号：US10482938B2
公开(公告)日：2019-11-19
申请号：US15691985
申请日：2017-08-31
发明人： Jong-Pil Son , Seong-Il O
摘要： A semiconductor memory device and method of operation that is capable of reducing disturbance of adjacent word lines. A memory cell array includes a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines. A first word-line, which is selected in response to an access address received from the memory controller, is enabled in response to a first command received from a memory controller, and the first word-line is disabled internally in the semiconductor memory device or in response to a disable command received from the memory controller after a reference time interval elapses. The reference time interval starts from a first time point when the first command is applied to the semiconductor memory device, and corresponds to a time interval equal to or greater than a row active time interval of the semiconductor memory device.
-
12.发明授权公开(公告)号：US10090066B2
公开(公告)日：2018-10-02
申请号：US15696794
申请日：2017-09-06
发明人： Sang-Uhn Cha , Hoi-Ju Chung , Jong-Pil Son , Kwang-Il Park , Seong-Jin Jang
摘要： A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.
-
13.发明授权Method of operating memory device and methods of writing and reading data in memory device 有权操作存储器件的方法和在存储器件中写入和读取数据的方法公开(公告)号：US09589674B2
公开(公告)日：2017-03-07
申请号：US14305095
申请日：2014-06-16
发明人： Jong-Pil Son , Young-Soo Sohn , Uk-Song Kang , Chul-Woo Park , Jung-Hwan Choi , Won-Il Bae , Kyo-Min Sohn
CPC分类号： G11C29/52 , G06F11/1048 , G11C2029/0411
摘要： In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word.
摘要翻译： 在操作存储器件的方法中，接收来自存储器控制器的命令和第一地址。 从存储器件的存储单元阵列读取包括对应于第一地址的第一组数据，对应于第二地址的第二组数据和读取奇偶校验数据的读码字。 通过使用基于读取的线字的ECC电路的操作错误检查和校正（ECC）来生成校正的数据。
-
公开(公告)号：US09235466B2
公开(公告)日：2016-01-12
申请号：US13915179
申请日：2013-06-11
发明人： Young-Soo Sohn , Chul-Woo Park , Jong-Pil Son , Jung-bae Lee
CPC分类号： G06F11/1012 , G06F11/10 , G06F11/1024 , G06F11/1048 , G06F11/106 , G11C2029/0411 , H03M13/3707
摘要： An error correction apparatus includes an error correction circuit configured to selectively perform error correction on a portion of data that is at least one of written to and read from a plurality of memory cells of a memory device. The portion of data is at least one of written to and read from a subset of the plurality of memory cells, and the subset includes only fail cells among the plurality of memory cells. The error correction apparatus further includes a fail address storage circuit configured to store address information for the fail cells.
摘要翻译： 纠错装置包括：纠错电路，被配置为对存储器件的多个存储单元的至少一个写入和读出的数据的一部分进行选择性地执行纠错。 数据的部分是从多个存储器单元的子集写入和读出中的至少一个，并且该子集仅包括多个存储器单元中的故障单元。 误差校正装置还包括故障地址存储电路，其被配置为存储故障单元的地址信息。
-
公开(公告)号：US09087614B2
公开(公告)日：2015-07-21
申请号：US14087167
申请日：2013-11-22
发明人： Jong-Pil Son , Uk-Song Kang , Chul-Woo Park , Young-Soo Sohn
CPC分类号： G11C29/4401 , G06F11/1048 , G11C5/04 , G11C29/808 , G11C2029/0409 , G11C2029/0411
摘要： In one example embodiment, a memory module includes a plurality of memory devices and a buffer chip configured to manage the plurality of memory device. The buffer chip includes a memory management unit having an error correction unit configured to perform error correction operation on each of the plurality of memory devices. Each of the plurality of memory devices includes at least one spare column that is accessible by the memory management unit, and the memory management unit is configured to correct errors of the plurality of memory devices by selectively using the at least one spare column based on an error correction capability of the error correction unit.
摘要翻译： 在一个示例实施例中，存储器模块包括多个存储器件和被配置为管理多个存储器件的缓冲器芯片。 缓冲器芯片包括具有错误校正单元的存储器管理单元，该单元被配置为对多个存储器件中的每一个进行纠错操作。 多个存储器设备中的每一个包括至少一个可由存储器管理单元访问的备用列，并且存储器管理单元被配置为通过有选择地使用至少一个备用列来校正多个存储器件的错误， 纠错单元的纠错能力。
-
16.发明授权公开(公告)号：US09007856B2
公开(公告)日：2015-04-14
申请号：US13804690
申请日：2013-03-14
发明人： Jong-Pil Son , Jae-Sung Kim , Uk-Song Kang , Young-Soo Sohn
CPC分类号： G11C29/04 , G11C29/806 , G11C29/808 , G11C2029/4402
摘要： A repair control circuit of controlling a repair operation of a semiconductor memory device includes a row matching block and a column matching block. The row matching block stores fail group information indicating one or more fail row groups among a plurality of row groups. The row groups are determined by grouping a plurality of row addresses corresponding to a plurality of wordlines. The row matching block generates a group match signal based on input row address and the fail group information, such that the group match signal indicates the fail row group including the input row address. The column matching block stores fail column addresses of the fail memory cells, and generates a repair control signal based on input column address, the group match signal and the fail column addresses, such that the repair control signal indicates whether the repair operation is executed or not.
摘要翻译： 控制半导体存储器件的修复操作的修复控制电路包括行匹配块和列匹配块。 行匹配块存储指示多个行组中的一个或多个故障行组的故障组信息。 通过对与多个字线对应的多个行地址进行分组来确定行组。 行匹配块基于输入行地址和故障组信息生成组匹配信号，使得组匹配信号指示包括输入行地址的故障行组。 列匹配块存储故障存储器单元的故障列地址，并且基于输入列地址，组匹配信号和故障列地址生成修复控制信号，使得修复控制信号指示是否执行修复操作或 不。
-
公开(公告)号：US09792978B2
公开(公告)日：2017-10-17
申请号：US15341245
申请日：2016-11-02
发明人： Jong-Pil Son , Ho-Young Song
IPC分类号： G11C16/06 , G11C11/4093 , G11C11/4091 , G11C11/4096 , G11C11/406 , G11C11/408 , G06F3/06
CPC分类号： G11C11/4093 , G06F3/061 , G06F3/065 , G06F3/0656 , G06F3/0659 , G06F3/0673 , G11C7/1045 , G11C7/106 , G11C7/1087 , G11C11/40607 , G11C11/4087 , G11C11/4091 , G11C11/4096
摘要： A semiconductor memory device includes a memory cell array and a first buffer. The memory cell array includes a plurality of bank arrays. Each of the plurality of bank arrays includes a plurality of memory cells. The memory cell array and the first buffer are configured for performing a first internal read operation, which represents operations of retrieving first data from a first region of the memory cell array and of storing the first data into the first buffer, based on a first read command and a first read address. The first internal read operation is performed based on a deterministic interface in which the first data is stored into the first buffer within a predetermined first duration after the first read command is received and a generation of a first acknowledgement signal is unnecessary after storing the first data into the first buffer is completed.
-
公开(公告)号：US09711205B2
公开(公告)日：2017-07-18
申请号：US14874568
申请日：2015-10-05
发明人： Jong-Pil Son , Chul-Woo Park , Young-Soo Sohn
CPC分类号： G11C11/40615 , G06F12/0246 , G06F2212/7201 , G11C11/005 , G11C29/28 , G11C2029/0409 , G11C2029/4402 , G11C2211/4061
摘要： A use time managing method of a semiconductor device may include (1) measuring an amount of accumulated operation time of the semiconductor device and when the amount is reached to a predetermined value, generating a unit storage activation signal; (2) repeating step (1) to generate one or more additional unit storage activation signals, thereby generating a plurality of unit storage activation signals, wherein the predetermined values are different for each repeating step; (3) storing data indicating each occurrence of generating the unit storage activation signals; and (4) detecting use time of the semiconductor device based on the cumulatively stored data.
-
公开(公告)号：US09558805B2
公开(公告)日：2017-01-31
申请号：US14083033
申请日：2013-11-18
发明人： Uk-Song Kang , Chul-Woo Park , Hak-Soo Yu , Jong-Pil Son
IPC分类号： G06F13/00 , G11C11/406 , G11C11/408
CPC分类号： G11C11/40607 , G11C11/40603 , G11C11/40622 , G11C11/4087
摘要： A memory module includes a plurality of memory devices and a buffer chip. The buffer chip manages the memory devices. The buffer chip includes a refresh control circuit that groups a plurality of memory cell rows of the memory devices into a plurality of groups according to a data retention time of tire memory cell rows. The buffer chip selectively refreshes each of the plurality of groups in each of a plurality of refresh time regions that are periodically repeated and applies respective refresh periods to the plurality of groups, respectively.
摘要翻译： 存储器模块包括多个存储器件和缓冲器芯片。 缓冲芯片管理存储器件。 缓冲芯片包括根据轮胎存储单元行的数据保持时间将存储器件的多个存储单元行分组成多个组的刷新控制电路。 缓冲器芯片有选择地刷新周期性地重复的多个刷新时间区域中的每一个中的多个组中的每一个，并将各个刷新周期分别应用于多个组。
-
20.发明授权Memory device selecting different column selection lines based on different offset values and memory system including the same 有权存储器件根据不同的偏移值选择不同的列选择线，包括相同的存储器系统公开(公告)号：US09064546B2
公开(公告)日：2015-06-23
申请号：US14069188
申请日：2013-10-31
发明人： Jong-Pil Son , Young-Soo Sohn , Chul-Woo Park , Cheol-Heui Park
CPC分类号： G11C8/06 , G11C7/12 , G11C8/10 , G11C16/24 , G11C29/18 , G11C2029/1204 , G11C2029/1806
摘要： A memory device may be provided which includes a memory cell array including a plurality of sub arrays each sub array having a plurality of memory cells connected to bit lines; an address buffer configured to receive a row address and a column address; and a column decoder configured to receive the column address from the address buffer and, for each of the sub arrays, to select a column selection line corresponding to the column address, from among a plurality of column selection lines, based on different offset values applied to the sub arrays, respectively. The selected column selection lines correspond to bit lines having different physical locations, respectively, according to the different offset values.
摘要翻译： 可以提供一种存储器件，其包括包括多个子阵列的存储单元阵列，每个子阵列具有连接到位线的多个存储器单元; 配置为接收行地址和列地址的地址缓冲器; 以及列解码器，被配置为从地址缓冲器接收列地址，并且对于每个子阵列，基于应用的不同偏移值从多个列选择线中选择与列地址对应的列选择线 分别到子阵列。 所选择的列选择线分别对应于具有不同物理位置的位线，根据不同的偏移值。
-
-
-
-
-
-
-
-
-
搜索结果
20 条记录 (耗时 0.03 秒)
