公开(公告)号：US06403481B1

公开(公告)日：2002-06-11

申请号：US09371221

申请日：1999-08-10

申请人： Tetsuo Matsuda ,  Hisashi Kaneko

发明人： Tetsuo Matsuda ,  Hisashi Kaneko

IPC分类号： H01L214763

CPC分类号： H01L21/76858 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76886 ,  H01L2221/1089

摘要： A film formation method for manufacture of a semiconductor device includes the steps of forming a first metal film as a continuous film on a substrate, forming a second metal film as discontinuous films on the substrate formed with the first metal film, and forming a third metal film by plating on the substrate formed with the first and second metal films.

摘要翻译： 用于制造半导体器件的成膜方法包括以下步骤：在基板上形成作为连续膜的第一金属膜，在形成有第一金属膜的基板上形成作为不连续膜的第二金属膜，以及形成第三金属 通过在由第一和第二金属膜形成的基板上电镀。

公开(公告)号：US06348402B1

公开(公告)日：2002-02-19

申请号：US09526880

申请日：2000-03-16

申请人： Takashi Kawanoue ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Tadashi Iijima

发明人： Takashi Kawanoue ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Tadashi Iijima

IPC分类号： H01L214763

CPC分类号： H01L21/76846 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76888 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A groove or hole is formed in an insulating layer formed on a semiconductor substrate, and a first conductive layer including a first metal element is formed on a surface of the insulating layer. By oxidizing the first conductive layer, an oxide layer of the first metal element is formed on a surface of the first conductive layer. A second conductive layer including a second metal element having a free energy of oxide formation lower than that of the first metal element is deposited thereon. By reducing the oxide layer of the first metal element by the second metal element, an oxide layer of the second metal element is formed at the interface between the first conductive layer and the second conductive layer. Further, an interconnection is buried in the groove or hole of the insulating layer. Thereby, a thin second metal oxide layer having excellent barrier properties against an interconnection material and excellent adhesion to the interconnection material can be selectively formed with a uniform thickness on the surface of the first conductive layer used as a barrier metal layer of the interconnection.

摘要翻译： 在形成于半导体衬底上的绝缘层中形成沟槽，在绝缘层的表面上形成包括第一金属元件的第一导电层。 通过氧化第一导电层，在第一导电层的表面上形成第一金属元素的氧化物层。 在其上沉积包括具有低于第一金属元素的自由能的氧化物形成的第二金属元素的第二导电层。 通过由第二金属元件还原第一金属元件的氧化物层，在第一导电层和第二导电层之间的界面处形成第二金属元素的氧化物层。 此外，互连被埋在绝缘层的凹槽或孔中。 由此，可以在用作互连的阻挡金属层的第一导电层的表面上选择性地形成具有优良的互连材料阻隔性和对互连材料的优异粘附性的薄的第二金属氧化物层。

公开(公告)号：US5679610A

公开(公告)日：1997-10-21

申请号：US356541

申请日：1994-12-15

申请人： Tetsuo Matsuda ,  Katsuya Okumura

发明人： Tetsuo Matsuda ,  Katsuya Okumura

IPC分类号： H01L21/3205 ,  H01L21/3105 ,  H01L21/31

CPC分类号： H01L21/31051

摘要： The present invention relates to a simple, low cost planarization technique whereby physical pressure is used to planarize the surface of a semiconductor device. The method of the present invention planarizes a semiconductor workpiece surface and results in an increase in the productivity of the processing steps that follow. In effect, the present invention applies physical pressure to flatten the surface layers of a semiconductor workpiece. The present invention is particularly adapted for use in planarizing surface layers made of plastic materials.

摘要翻译： 本发明涉及一种简单的低成本平面化技术，其中使用物理压力来平坦化半导体器件的表面。 本发明的方法对半导体工件表面进行了平面化，并导致随后的加工步骤的生产率的提高。 实际上，本发明应用物理压力来平坦化半导体工件的表面层。 本发明特别适用于平坦化由塑料材料制成的表面层。

公开(公告)号：US4923715A

公开(公告)日：1990-05-08

申请号：US358493

申请日：1989-05-30

申请人： Tetsuo Matsuda ,  Iwao Kunishima

发明人： Tetsuo Matsuda ,  Iwao Kunishima

IPC分类号： C23C8/24 ,  C23C16/34 ,  C23C16/44

CPC分类号： C23C16/34 ,  C23C16/44 ,  C23C16/4404 ,  C23C8/24

摘要： A method for the formation of a thin, high melting-point metal film such as W, on a substrate surface, by means of CVD, is disclosed herein. In this method, the inner wall of the CVD reaction tube and the surface of the at least part of the fittings disposed therewithin are covered with a metal nitride film, in the process of performing the CVD operation. The method permits the formation of a high quality film, and also prevents the deposition of the high melting-point metal on the inner wall of the reaction chamber, even if the CVD operation is repeatedly performed over a long period of time.

摘要翻译： 本文公开了通过CVD在衬底表面上形成诸如W的薄的高熔点金属膜的方法。 在该方法中，在进行CVD操作的过程中，CVD反应管的内壁和布置在其中的配件的至少一部分的表面被金属氮化物膜覆盖。 该方法允许形成高质量的膜，并且即使在长时间反复进行CVD操作，也可以防止高熔点金属沉积在反应室的内壁上。

公开(公告)号：US08431992B2

公开(公告)日：2013-04-30

申请号：US13023210

申请日：2011-02-08

申请人： Kenichi Tokano ,  Tetsuo Matsuda ,  Wataru Saito

发明人： Kenichi Tokano ,  Tetsuo Matsuda ,  Wataru Saito

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

摘要： A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

摘要翻译： 第一导电类型的单晶半导体层设置在半导体衬底的表面上。 在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。 外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。 多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

公开(公告)号：US20110133278A1

公开(公告)日：2011-06-09

申请号：US13023210

申请日：2011-02-08

申请人： Kenichi TOKANO ,  Tetsuo Matsuda ,  Wataru Saito

发明人： Kenichi TOKANO ,  Tetsuo Matsuda ,  Wataru Saito

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

摘要： A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

摘要翻译： 第一导电类型的单晶半导体层设置在半导体衬底的表面上。 在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。 外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。 多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

公开(公告)号：US20090302373A1

公开(公告)日：2009-12-10

申请号：US12543165

申请日：2009-08-18

申请人： Kenichi TOKANO ,  Tetsuo Matsuda ,  Wataru Saito

发明人： Kenichi TOKANO ,  Tetsuo Matsuda ,  Wataru Saito

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

摘要： A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

摘要翻译： 第一导电类型的单晶半导体层设置在半导体衬底的表面上。 在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。 外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。 多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

公开(公告)号：US20060043480A1

公开(公告)日：2006-03-02

申请号：US10991433

申请日：2004-11-19

申请人： Masanobu Tsuchitani ,  Tetsuo Matsuda ,  Hideki Okumura ,  Atsuko Yamashita

发明人： Masanobu Tsuchitani ,  Tetsuo Matsuda ,  Hideki Okumura ,  Atsuko Yamashita

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/66712 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/42368 ,  H01L29/7811

摘要： A semiconductor device comprises a semiconductor layer which includes a terminate end part and a cell formation part that is surrounded by this end part, and a plurality of guard rings each of which is formed at the end part to surround the cell formation part. These guard rings are made shallower and smaller in width as they get near to the guard ring that resides at the outside position.

摘要翻译： 半导体器件包括半导体层，其包括终端部分和由该端部部分包围的电池形成部分，以及多个保护环，每个保护环形成在端部处以围绕电池形成部分。 这些保护环的宽度越来越小，因为它们靠近位于外部位置的防护环。

公开(公告)号：US20050145482A1

公开(公告)日：2005-07-07

申请号：US10973350

申请日：2004-10-27

申请人： Hidenao Suzuki ,  Koji Mishima ,  Hiroyuki Kanda ,  Kazufumi Nomura ,  Kunihito Ide ,  Kazuyuki Yahiro ,  Hiroshi Toyoda ,  Tetsuo Matsuda

发明人： Hidenao Suzuki ,  Koji Mishima ,  Hiroyuki Kanda ,  Kazufumi Nomura ,  Kunihito Ide ,  Kazuyuki Yahiro ,  Hiroshi Toyoda ,  Tetsuo Matsuda

IPC分类号： C25D7/12 ,  C25D17/00 ,  C25D17/06 ,  C25D21/10 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/68 ,  H01L21/683

CPC分类号： H01L21/2885 ,  C25D7/123 ,  C25D17/001 ,  C25D17/06

摘要： An apparatus and a method for processing substrate are generally used for apparatuses for wet-type process of substrate, such as an electrolytic processing apparatus for use in forming interconnects by embedding a metal such as copper (Cu) or the like in fine interconnect patterns (recesses) that are formed in a substrate such as a semiconductor wafer and for use in forming bumps for electrical connections. The substrate processing apparatus includes: a substrate holder for holding a substrate; a first electrode for contacting the substrate to supply electricity to a processing surface of the substrate; a second electrode disposed so as to face the processing surface of the substrate held by the substrate holder; and a processing liquid supply section for supplying a processing liquid into the space between the processing surface of the substrate held by the substrate holder and the second electrode, wherein the substrate holder is designed to rotate the substrate during processing in such a manner that acceleration and slowdown and/or normal rotation and reverse rotation are repeated.

摘要翻译： 用于处理衬底的装置和方法通常用于衬底的湿式处理装置，例如通过将金属（例如铜）（Cu）等嵌入到精细互连图案中而形成互连件的电解处理装置 凹部），其形成在诸如半导体晶片的基板中，并且用于形成用于电连接的凸块。 基板处理装置包括：用于保持基板的基板保持件; 第一电极，用于接触所述衬底以向所述衬底的处理表面供电; 第二电极，其设置成面对由所述基板保持器保持的所述基板的处理表面; 以及处理液体供应部分，用于将处理液体供应到由基板保持器保持的基板的处理表面与第二电极之间的空间中，其中基板保持器设计成在加工期间使基板旋转， 重复减速和/或正常旋转和反向旋转。

公开(公告)号：US06897143B2

公开(公告)日：2005-05-24

申请号：US10600568

申请日：2003-06-23

申请人： Hiroshi Toyoda ,  Hiroyuki Yano ,  Gaku Minamihaba ,  Dai Fukushima ,  Tetsuo Matsuda ,  Hisashi Kaneko

发明人： Hiroshi Toyoda ,  Hiroyuki Yano ,  Gaku Minamihaba ,  Dai Fukushima ,  Tetsuo Matsuda ,  Hisashi Kaneko

IPC分类号： H01L21/304 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC分类号： H01L21/76846 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a cap film comprises a first polishing step of performing a polishing operation at selectivity of R1 (=removal rate for the cap film/removal rate for the insulating film), and a second polishing step of performing a polishing operation at selectivity of R2 (=removal rate for the cap film/removal rate for the insulating film). Each of the polishing operations is performed by using a slurry having the condition of R1>R2. By performing the polishing operations at different selectivity, the cap film free from problems such as dishing of the cap film and the residual cap film on side walls of a recess is formed. Consequently, a semiconductor device having an excellent RC characteristic can be provided.

摘要翻译： 形成盖膜的方法包括以R 1的选择性（=盖膜的去除速率/绝缘膜的去除速率）进行抛光操作的第一抛光步骤，以及进行抛光操作的第二抛光步骤 R 2的选择性（=盖膜的去除率/绝缘膜的去除率）。 通过使用条件为R 1> R 2的浆料进行每次研磨操作。 通过以不同的选择性进行抛光操作，形成了帽膜没有诸如凹陷的盖膜和残留帽膜之间的问题。 因此，可以提供具有优异RC特性的半导体器件。