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    Semiconductor device having Schmitt trigger NAND circuit and Schmitt trigger inverter
    11.
    发明授权
    Semiconductor device having Schmitt trigger NAND circuit and Schmitt trigger inverter 有权
    具有施密特触发器NAND电路和施密特触发器的半导体器件

    公开(公告)号：US09245589B2

    公开(公告)日：2016-01-26

    申请号：US14217793

    申请日：2014-03-18

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Takeshi Aoki ,  Yoshiyuki Kurokawa ,  Munehiro Kozuma

    IPC: G11C5/06 ,  G11C7/10

    CPC classification number: G11C5/06 ,  G11C7/1051 ,  G11C7/1057 ,  G11C11/24 ,  G11C14/0054

    Abstract: A nonvolatile semiconductor device which can be driven at low voltage is provided. A nonvolatile semiconductor device with low power consumption is provided. A Schmitt trigger NAND circuit and a Schmitt trigger inverter are included. Data is held in a period when the supply of power supply voltage is continued, and a potential corresponding to the data is stored at a node electrically connected to a capacitor before a period when the supply of power supply voltage is stopped. By utilizing a change in channel resistance of a transistor whose gate is connected to the node, the data is restored in response to the restart of the supply of power supply voltage.

    Abstract translation: 提供了可以以低电压驱动的非易失性半导体器件。 提供了具有低功耗的非易失性半导体器件。 包括施密特触发器NAND电路和施密特触发器反相器。 数据保持在电源电压继续供给的期间，与电源相对应的电位存储在与电容器电连接的节点上，在供给电源电压停止的期间。 通过利用其栅极连接到节点的晶体管的沟道电阻的变化，响应于电源电压的重新启动恢复数据。

    Touch panel
    12.
    发明授权
    Touch panel 有权
    触控面板

    公开(公告)号：US09207798B2

    公开(公告)日：2015-12-08

    申请号：US14280851

    申请日：2014-05-19

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hikaru Tamura ,  Munehiro Kozuma

    IPC: G06F3/041 ,  G06F3/033 ,  G09G3/30 ,  H01L21/00 ,  H01J1/62 ,  H03K17/96 ,  H03K17/975

    CPC classification number: G06F3/0412 ,  G06F3/0414 ,  H03K17/962 ,  H03K17/975 ,  H03K2217/96015 ,  H03K2217/96046 ,  H03K2217/9653

    Abstract: A touch sensor (touch panel) which can be formed over the same substrate as a display portion is provided. Alternatively, a touch sensor (touch panel) which does not cause degradation in the quality of an image displayed on a display portion is provided. The touch panel includes a light-emitting element and a microstructure in which a pair of electrodes facing each other is isolated with an insulating material. As the insulating material, an elastic material or a material having a hole is used so that a filler layer formed using the insulating material can be deformed when a movable portion operates. It is preferable to use a material which is softened or hardened by certain treatment (e.g., heat treatment or chemical treatment) after formation.

    Abstract translation: 提供了可以在与显示部分相同的基板上形成的触摸传感器（触摸面板）。 或者，提供不会导致显示在显示部分上的图像的质量下降的触摸传感器（触摸面板）。 触摸面板包括发光元件和其中彼此面对的一对电极用绝缘材料隔离的微结构。 作为绝缘材料，使用弹性材料或具有孔的材料，使得当可动部分操作时，使用绝缘材料形成的填充层可以变形。 优选在形成后通过某种处理（例如热处理或化学处理）使用软化或硬化的材料。

    Programmable logic device
    14.
    发明授权
    Programmable logic device 有权
    可编程逻辑器件

    公开(公告)号：US09065438B2

    公开(公告)日：2015-06-23

    申请号：US14305434

    申请日：2014-06-16

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takeshi Aoki ,  Yoshiyuki Kurokawa ,  Munehiro Kozuma ,  Takashi Nakagawa

    IPC: H03K19/0185 ,  H03K19/00

    CPC classification number: H03K19/0013 ,  H03K19/018585

    Abstract: Data of a register in a programmable logic element is retained. A volatile storage circuit and a nonvolatile storage circuit are provided in a register of a programmable logic element whose function can be changed in response to a plurality of context signals. The nonvolatile storage circuit includes nonvolatile storage portions for storing data in the register. The number of nonvolatile storage portions corresponds to the number of context signals. With such a structure, the function can be changed each time context signals are switched and data in the register that is changed when the function is changed can be backed up to the nonvolatile storage portion in each function. In addition, the function can be changed each time context signals are switched and the data in the register that is backed up when the function is changed can be recovered to the volatile storage circuit.

    Abstract translation: 可编程逻辑元件中寄存器的数据被保留。 易失性存储电路和非易失性存储电路设置在可编程逻辑元件的寄存器中，该可编程逻辑元件的功能可以响应于多个上下文信号而改变。 非易失性存储电路包括用于将数据存储在寄存器中的非易失性存储部分。 非易失性存储部分的数量对应于上下文信号的数量。 通过这样的结构，可以在每次上下文信号切换时改变功能，并且在功能改变时改变的寄存器中的数据可以备份到每个功能中的非易失性存储部分。 此外，每当上下文信号被切换并且功能改变时备份的寄存器中的数据可以被恢复到易失性存储电路时，可以改变该功能。

    Programmable logic device and semiconductor device
    15.
    发明授权
    Programmable logic device and semiconductor device 有权
    可编程逻辑器件和半导体器件

    公开(公告)号：US08952723B2

    公开(公告)日：2015-02-10

    申请号：US14166936

    申请日：2014-01-29

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takeshi Aoki ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa ,  Munehiro Kozuma

    IPC: H03K19/094 ,  H01L25/00 ,  H03K19/0175

    CPC classification number: H03K19/1776 ,  H03K19/017581

    Abstract: To provide a PLD having a reduced circuit area and an increased operation speed. In the circuit structure, a gate of a transistor provided between an input terminal and an output terminal of a programmable switch element is in an electrically floating state in a period when a signal is input to the programmable switch element. The structure enables the voltage of a gate to be increased by a boosting effect in response to a signal supplied from programmable logic elements, suppressing a reduction in amplitude voltage. This can reduce a circuit area by a region occupied by a booster circuit such as a pull-up circuit and increase operation speed.

    Abstract translation: 提供具有减小的电路面积和增加的操作速度的PLD。 在电路结构中，设置在可编程开关元件的输入端子和输出端子之间的晶体管的栅极在信号被输入到可编程开关元件的时段内处于电浮动状态。 该结构使得能够响应于从可编程逻辑元件提供的信号的升压效应来增加栅极的电压，从而抑制幅度电压的降低。 这可以通过诸如上拉电路的升压电路占据的区域来减小电路面积，并且增加操作速度。

    PROGRAMMABLE LOGIC DEVICE AND SEMICONDUCTOR DEVICE
    16.
    发明申请
    PROGRAMMABLE LOGIC DEVICE AND SEMICONDUCTOR DEVICE 有权
    可编程逻辑器件和半导体器件

    公开(公告)号：US20140225641A1

    公开(公告)日：2014-08-14

    申请号：US14170825

    申请日：2014-02-03

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Munehiro Kozuma ,  Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Takeshi Aoki

    IPC: H03K19/177

    CPC classification number: H03K19/0013 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/7869 ,  H03K19/09441 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17748 ,  H03K19/1776

    Abstract: A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.

    Abstract translation: 可编程逻辑器件包括多个可编程逻辑元件（PLE），其电连接由第一配置数据来控制。 每个PLE包括LUT，其中输入信号的逻辑电平和输出信号的逻辑电平之间的关系由第二配置数据确定，输入LUT的输出信号的FF和MUX 。 MUX包括至少两个开关，每个开关包括第一和第二晶体管。 包括第三配置数据的信号通过第一晶体管输入到第二晶体管的栅极。 LUT的输出信号或FF的输出信号被输入到第二晶体管的源极和漏极之一。

    Semiconductor device and electronic device
    17.
    发明授权
    Semiconductor device and electronic device 有权

    公开(公告)号：US12136465B2

    公开(公告)日：2024-11-05

    申请号：US17922659

    申请日：2021-05-06

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takeshi Aoki ,  Yoshiyuki Kurokawa ,  Munehiro Kozuma ,  Takuro Kanemura ,  Tatsunori Inoue

    IPC: G11C5/06 ,  G11C5/10 ,  G11C11/22 ,  H01L29/66 ,  H01L29/78 ,  H10B53/30

    Abstract: A semiconductor device with a small circuit area and low power consumption is provided. The semiconductor device includes first to fourth cells, a current mirror circuit, and first to fourth wirings, and the first to fourth cells each include a first transistor, a second transistor, and a capacitor. In each of the first to fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. The first wiring is electrically connected to first terminals of the second transistors in the first cell and the second cell, the second wiring is electrically connected to first terminals of the second transistors in the third cell and the fourth cell, the third wiring is electrically connected to second terminals of the capacitors in the first cell and the third cell, and the fourth wiring is electrically connected to second terminals of the capacitors in the second cell and the fourth cell. The current mirror circuit is electrically connected to the first wiring and the second wiring.

    Semiconductor device
    18.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12080377B2

    公开(公告)日：2024-09-03

    申请号：US17802281

    申请日：2021-03-04

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yuki Okamoto ,  Tatsuya Onuki ,  Munehiro Kozuma ,  Takanori Matsuzaki

    IPC: G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  H01L29/786 ,  H10B12/00

    CPC classification number: G11C7/1096 ,  G11C7/12 ,  G11C8/08 ,  H01L29/7869 ,  H10B12/31 ,  H10B12/50

    Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of arithmetic blocks each including an arithmetic circuit portion and a memory circuit portion. The arithmetic circuit portion and the memory circuit portion are electrically connected to each other. The arithmetic circuit portion and the memory circuit portion have an overlap region. The arithmetic circuit portion includes, for example, a Si transistor, and the memory circuit portion includes, for example, an OS transistor. The arithmetic circuit portion has a function of performing product-sum operation. The memory circuit portion has a function of retaining weight data. A first driver circuit has a function of writing the weight data to the memory circuit portion. The weight data is written to all the memory circuit portions included in the same column with the use of the first driver circuit.

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