公开(公告)号：US20170133064A1

公开(公告)日：2017-05-11

申请号：US15341707

申请日：2016-11-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shuhei NAGATSUKA ,  Tomokazu YOKOI ,  Naoaki TSUTSUI ,  Kazuaki OHSHIMA ,  Tatsuya ONUKI

IPC: G11C7/06 ,  G11C7/10 ,  G11C8/10 ,  G11C7/12 ,  H01L27/115 ,  G11C5/06

CPC classification number: G11C7/065 ,  G11C5/063 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C8/14 ,  G11C11/403 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4094 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/30 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582

Abstract: A semiconductor device or a memory device with a reduced area, a large storage capacity, a high-speed operation, or low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, a first wiring, a second wiring, a sense amplifier circuit, a decoder, a step-up circuit, a level shifter, and a buffer circuit. The first wiring is electrically connected to the buffer circuit and a second gate electrode of the first transistor. The second wiring is electrically connected to the sense amplifier circuit and the drain electrode of the second transistor. The capacitor is electrically connected to the drain electrode of the first transistor and the source electrode of the second transistor.

公开(公告)号：US20160253236A1

公开(公告)日：2016-09-01

申请号：US15047729

申请日：2016-02-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Naoaki TSUTSUI

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/106 ,  G11C29/52

Abstract: A memory system that includes an error check and correct (ECC) circuit is provided. The memory system includes a memory, the ECC circuit, and a processor. The processor controls the entire operation of the memory system. The memory includes a user data region and a management region. The management region stores access information of each of blocks in the user data region as a management table. The value of the access information is either a first value indicating that the number of access times is 0 or a second value indicating that the number of access times is greater than or equal to 1. When the value of the access information of the block is the first value, the circuit checks and corrects an error of data read from the block. When the value of the access information of the block is the second value, the circuit does not check and correct an error of data read from the block.

Abstract translation: 提供了包括错误检查和正确（ECC）电路的存储器系统。 存储器系统包括存储器，ECC电路和处理器。 处理器控制存储系统的整个操作。 存储器包括用户数据区域和管理区域。 管理区域将用户数据区域中的每个块的访问信息存储为管理表。 访问信息的值是指示访问次数为0的第一值或指示访问次数大于或等于1的第二值。当块的访问信息的值为 第一个值，电路检查并纠正从块读取的数据的错误。 当块的访问信息的值是第二个值时，电路不会检查并纠正从块读取的数据的错误。

公开(公告)号：US20160233865A1

公开(公告)日：2016-08-11

申请号：US15014081

申请日：2016-02-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hikaru TAMURA ,  Naoaki TSUTSUI ,  Atsuo ISOBE

IPC: H03K19/00 ,  H01L23/528 ,  H01L27/12 ,  H01L29/786 ,  H01L27/06 ,  H01L27/02 ,  H01L23/532

CPC classification number: H01L27/0207 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/0688 ,  H01L27/1207 ,  H01L27/1274 ,  H01L29/7869 ,  H03K19/0008

Abstract: To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element layer and a second element layer. A third wiring layer and a fourth wiring layer are stacked over the second element layer. Transistors of logic cells are provided in the first element layer. Wirings of the logic cells are provided in the first wiring layer or the second wiring layer. Input ports and output ports of the logic cells are provided in the third wiring layer. The input port of one of the logic cells is connected to the output port of another logic cell through the wiring of the third wiring layer or the fourth wiring layer. Connecting the logic cells through the wiring layers over the second element layer improves the efficiency of steps of arranging and connecting the logic cells.

Abstract translation: 提供包括堆叠的元件层的半导体器件。 第一布线层和第二布线层堆叠在第一元件层和第二元件层之间。 在第二元件层上堆叠第三布线层和第四布线层。 逻辑单元的晶体管设置在第一元件层中。 逻辑单元的布线设置在第一布线层或第二布线层中。 逻辑单元的输入端口和输出端口设置在第三布线层中。 一个逻辑单元的输入端口通过第三布线层或第四布线层的布线连接到另一逻辑单元的输出端口。 通过第二元件层上的布线层连接逻辑单元提高了布置和连接逻辑单元的步骤的效率。

公开(公告)号：US20150363136A1

公开(公告)日：2015-12-17

申请号：US14731940

申请日：2015-06-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru UESUGI ,  Tomoaki ATSUMI ,  Naoaki TSUTSUI ,  Hikaru TAMURA ,  Takahiko ISHIZU ,  Takuro OHMARU

IPC: G06F3/06 ,  G06F11/14

CPC classification number: G06F12/00 ,  G11C5/00 ,  H01L27/0688 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7782

Abstract: A semiconductor device including a register controller and a processor which includes a register is provided. The register includes a first circuit and a second circuit which includes a plurality of memory portions. The first circuit and the plurality of memory portions can store data by an arithmetic process of the processor. Which of the plurality of memory portions the data is stored in depends on a routine by which the data is processed. The register controller switches the routine in response to an interrupt signal. The register controller can make any one of the plurality of memory portions which corresponds to the routine store the data in the first circuit every time the routine is switched. The register controller can make data stored in any one of the plurality of memory portions which corresponds to the routine be stored in the first circuit every time the routine is switched.

Abstract translation: 提供一种包括寄存器控制器和包括寄存器的处理器的半导体器件。 寄存器包括第一电路和包括多个存储器部分的第二电路。 第一电路和多个存储器部分可以通过处理器的算术处理来存储数据。 存储数据的多个存储器部分中的哪一个取决于数据被处理的程序。 寄存器控制器响应中断信号切换程序。 寄存器控制器可以使每次该例程的多个存储器部分中的任何一个存储在第一电路中。 寄存器控制器可以在每次该例程被切换时使存储在与该程序相对应的多个存储器部分中的任何一个存储器中的数据存储在第一电路中。