公开(公告)号：US09343584B2

公开(公告)日：2016-05-17

申请号：US14819772

申请日：2015-08-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yusuke Nonaka ,  Takayuki Inoue ,  Masashi Tsubuku ,  Kengo Akimoto ,  Akiharu Miyanaga

IPC: H01L27/01 ,  H01L27/12 ,  H01L29/12 ,  H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/0392 ,  H01L29/786 ,  H01L29/24 ,  H01L21/02

CPC classification number: H01L29/7869 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/04 ,  H01L29/24 ,  H01L29/78603

Abstract: An object is to provide a semiconductor device including an oxide semiconductor film, which has stable electrical characteristics and high reliability. A stack of first and second material films is formed by forming the first material film (a film having a hexagonal crystal structure) having a thickness of 1 nm to 10 nm over an insulating surface and forming the second material film having a hexagonal crystal structure (a crystalline oxide semiconductor film) using the first material film as a nucleus. As the first material film, a material film having a wurtzite crystal structure (e.g., gallium nitride or aluminum nitride) or a material film having a corundum crystal structure (α-Al2O3, α-Ga2O3, In2O3, Ti2O3, V2O3, Cr2O3, or α-Fe2O3) is used.

公开(公告)号：US09105668B2

公开(公告)日：2015-08-11

申请号：US14508075

申请日：2014-10-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yusuke Nonaka ,  Takayuki Inoue ,  Masashi Tsubuku ,  Kengo Akimoto ,  Akiharu Miyanaga

IPC: H01L29/66 ,  H01L29/786 ,  H01L23/552 ,  H01L23/00

CPC classification number: H01L29/78606 ,  H01L23/552 ,  H01L23/564 ,  H01L29/04 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor film, which has stable electric characteristics and high reliability. A crystalline oxide semiconductor film is formed, without performing a plurality of steps, as follows: by utilizing a difference in atomic weight of plural kinds of atoms included in an oxide semiconductor target, zinc with low atomic weight is preferentially deposited on an oxide insulating film to form a seed crystal including zinc; and tin, indium, or the like with high atomic weight is deposited on the seed crystal while causing crystal growth. Further, a crystalline oxide semiconductor film is formed by causing crystal growth using a seed crystal with a hexagonal crystal structure including zinc as a nucleus, whereby a single crystal oxide semiconductor film or a substantially single crystal oxide semiconductor film is formed.

Abstract translation: 本发明的目的是制造具有稳定的电特性和高可靠性的氧化物半导体膜的半导体装置。 通过利用包含在氧化物半导体靶中的多种原子的原子量的差异，形成结晶氧化物半导体膜，而不进行多个步骤，优选将低原子量的锌沉积在氧化物绝缘膜上 形成包含锌的晶种; 并且具有高原子量的锡，铟等沉积在晶种上同时引起晶体生长。 此外，通过使用具有包含锌作为核的六方晶系结构的晶种进行晶体生长来形成结晶氧化物半导体膜，从而形成单晶氧化物半导体膜或大致单晶氧化物半导体膜。

公开(公告)号：US20150011048A1

公开(公告)日：2015-01-08

申请号：US14322555

申请日：2014-07-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tetsuhiro Tanaka ,  Takayuki Inoue ,  Yoshitaka Yamamoto ,  Hideomi Suzawa ,  Tamae Moriwaka

IPC: H01L29/66 ,  H01L29/423

CPC classification number: H01L29/4234 ,  H01L29/4908 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device in which the threshold value is controlled. Furthermore, to provide a semiconductor device in which a deterioration in electrical characteristics which becomes more noticeable as a transistor is miniaturized can be suppressed. The semiconductor device includes a first semiconductor film, a source electrode and a drain electrode electrically connected to the first semiconductor film, a gate insulating film, and a gate electrode in contact with the gate insulating film. The gate insulating film includes a first insulating film and a trap film, and charge is trapped in a charge trap state in an interface between the first insulating film and the trap film or inside the trap film.

Abstract translation: 提供其中控制阈值的半导体器件。 此外，为了提供一种半导体器件，其中可以抑制作为晶体管变得更显着的电特性的劣化小型化。 半导体器件包括与栅极绝缘膜接触的第一半导体膜，与第一半导体膜电连接的栅极绝缘膜和栅电极的源电极和漏电极。 栅极绝缘膜包括第一绝缘膜和陷阱膜，并且在第一绝缘膜和陷阱膜之间的界面内或捕获膜内部的电荷陷阱状态下捕获电荷。

公开(公告)号：US09893194B2

公开(公告)日：2018-02-13

申请号：US14476767

申请日：2014-09-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka Yamamoto ,  Tetsuhiro Tanaka ,  Takayuki Inoue ,  Hideomi Suzawa

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L29/49 ,  H01L27/12 ,  G11C16/04 ,  G11C16/34 ,  G11C11/24 ,  G11C7/04 ,  G11C14/00

CPC classification number: H01L29/7869 ,  G11C7/04 ,  G11C11/24 ,  G11C14/0054 ,  G11C16/0466 ,  G11C16/3404 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696 ,  H01L29/7881

Abstract: A method for adjusting threshold of a semiconductor device is provided. In a plurality of semiconductor devices each including a semiconductor, a source or drain electrode electrically in contact with the semiconductor, a gate electrode, and a charge trap layer between a gate electrode and the semiconductor, a state where the potential of the gate electrode is set higher than the potential of the source or drain electrode while the semiconductor devices are heated at 150° C. or higher and 300° C. or lower is kept for one second or longer to trap electrons in the charge trap layer, so that the threshold is increased and Icut is reduced. Here, the potential difference between the gate electrode and the source or drain electrode is set so that it is different between the semiconductor devices, and the thresholds of the semiconductor devices are adjusted to be appropriate to each purpose.

公开(公告)号：US09443592B2

公开(公告)日：2016-09-13

申请号：US14330481

申请日：2014-07-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Yasuhiko Takemura ,  Tetsuhiro Tanaka ,  Takayuki Inoue ,  Toshihiko Takeuchi ,  Yasumasa Yamane ,  Shunpei Yamazaki

IPC: H01L21/00 ,  G11C16/04 ,  G11C16/20 ,  H01L21/28 ,  H01L27/108 ,  H01L27/115

CPC classification number: G11C16/0466 ,  G11C16/20 ,  H01L21/28282 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/11568

Abstract: A manufacturing method of a semiconductor device in which the threshold is corrected is provided. In a semiconductor device including a plurality of transistors each includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit for supplying a signal to the gate electrode and a circuit for supplying a signal to the source or drain electrode are electrically separated from each other. The process is performed in the state where the potential of the former circuit is set higher than the potential of the latter circuit.

Abstract translation: 提供了其中校正阈值的半导体器件的制造方法。 在包括多个晶体管的半导体器件中，每个包括半导体，与半导体电连接的源电极或漏电极，栅电极和栅电极与半导体之间的电荷陷阱层，电子被俘获在电荷陷阱层 通过进行热处理，同时保持栅电极的电位高于源电极或漏电极的电位1秒以上。 通过该过程，阈值增加并且Icut减小。 用于向栅电极提供信号的电路和用于向源电极或漏电极提供信号的电路彼此电分离。 该处理在前一电路的电位被设置为高于后一电路的电位的状态下执行。

公开(公告)号：US09269822B2

公开(公告)日：2016-02-23

申请号：US14479623

申请日：2014-09-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka Yamamoto ,  Tetsuhiro Tanaka ,  Takayuki Inoue ,  Hideomi Suzawa ,  Yasuhiko Takemura

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  G11C16/00 ,  H01L29/788 ,  H01L29/49

CPC classification number: H01L29/7869 ,  G11C11/24 ,  G11C16/00 ,  G11C16/0466 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78696 ,  H01L29/7881

Abstract: A method for manufacturing a semiconductor device with adjusted threshold is provided. In a semiconductor device including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is provided, a charge trap layer provided between the first gate electrode and the semiconductor, and a gate insulating layer provided between the second gate electrode and the semiconductor, a threshold is increased by trapping electrons in the charge trap layer by keeping a potential of the first gate electrode at a potential higher than a potential of the source or drain electrode for 1 second or more while heating. After the threshold adjustment process, the first gate electrode is removed or insulated from other circuits. Alternatively, a resistor may be provided between the first gate electrode and other circuits.

Abstract translation: 提供一种用于制造具有调节阈值的半导体器件的方法。 在包括半导体，与半导体电连接的源电极或漏电极的半导体器件中，设置有半导体的第一栅电极和第二栅电极，设置在第一栅电极和半导体之间的电荷陷阱层，以及 设置在第二栅电极和半导体之间的栅极绝缘层，通过将第一栅电极的电位保持在高于源电极或漏电极的电位的电位为1，通过在电荷陷阱层中俘获电子来增加阈值 第二次或多次加热。 在阈值调整处理之后，第一栅电极被去除或与其它电路绝缘。 或者，可以在第一栅极电极和其它电路之间设置电阻器。

公开(公告)号：US20140319519A1

公开(公告)日：2014-10-30

申请号：US14330113

申请日：2014-07-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takayuki Inoue ,  Masashi Tsubuku ,  Suzunosuke Hiraishi ,  Junichiro Sakata ,  Erumu Kikuchi ,  Hiromichi Godo ,  Akiharu Miyanaga ,  Shunpei Yamazaki

IPC: H01L29/786 ,  H01L31/18 ,  H01L29/24 ,  H01L31/032

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/41733 ,  H01L31/032 ,  H01L31/18

Abstract: An oxide semiconductor layer in which “safe” traps exist exhibits two kinds of modes in photoresponse characteristics. By using the oxide semiconductor layer, a transistor in which light deterioration is suppressed to the minimum and the electric characteristics are stable can be achieved. The oxide semiconductor layer exhibiting two kinds of modes in photoresponse characteristics has a photoelectric current value of 1 pA to 10 nA inclusive. When the average time τ1 until which carriers are captured by the “safe” traps is large enough, there are two kinds of modes in photoresponse characteristics, that is, a region where the current value falls rapidly and a region where the current value falls gradually, in the result of a change in photoelectric current over time.

Abstract translation: “安全”陷阱存在的氧化物半导体层表现出光响应特性的两种模式。 通过使用氧化物半导体层，可以实现将光劣化抑制到最小并且电特性稳定的晶体管。 在光响应特性中表现出两种模式的氧化物半导体层具有1pA至10nA的光电流值。 当通过“安全”陷阱捕获载流子的平均时间τ1足够大时，光响应特性即电流值急剧下降的区域和电流值逐渐下降的区域有两种模式 在光电流随时间变化的结果中。