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    Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method
    11.
    发明授权
    Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method 有权
    使用热处理制造薄介电层的方法和使用该方法形成的半导体器件

    公开(公告)号：US07041557B2

    公开(公告)日：2006-05-09

    申请号：US10832952

    申请日：2004-04-27

    申请人： Sung-Taeg Kang ,  Jeong-Uk Han ,  Sung-Woo Park ,  Seung-Beom Yoon ,  Ji-Hoon Park ,  Bo-Young Seo

    发明人： Sung-Taeg Kang ,  Jeong-Uk Han ,  Sung-Woo Park ,  Seung-Beom Yoon ,  Ji-Hoon Park ,  Bo-Young Seo

    IPC分类号： H01L21/366

    CPC分类号： H01L21/0214 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/28273 ,  H01L21/3144

    摘要： In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range. In addition, the size of the transistor and resulting storage cell can be minimized and the need for a high-voltage region in the circuit is mitigated, since, assuming a lowered programming voltage, pumping circuitry is not required.

    摘要翻译： 在根据该方法形成的半导体器件和半导体器件的形成方法中，在下导电层和上导电层之间设置有薄的电介质层。 在一个实施例中，薄介电层包括栅极间电介质层，下导电层包括浮动栅极，上介电层包括晶体管的控制栅极，例如非易失性存储单元晶体管。 使用导致下面的浮置栅极的表面粗糙度降低的热处理工艺形成薄介电层，并且导致在浮动栅极上形成薄的氧氮化硅层。 以这种方式，薄介电层提供在下浮动栅极和上控制栅极之间增加的电容耦合。 这也导致降低的编程电压，擦除晶体管的电压和读取电压，同时将阈值电压保持在期望的范围内。 此外，晶体管和所得到的存储单元的尺寸可以被最小化，并且减轻了对电路中的高电压区域的需要，因为假设降低的编程电压，不需要泵浦电路。

    Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method
    12.
    发明授权
    Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method 有权
    使用热处理制造薄介电层的方法和使用该方法形成的半导体器件

    公开(公告)号：US07190024B2

    公开(公告)日：2007-03-13

    申请号：US11329217

    申请日：2006-01-10

    申请人： Sung-Taeg Kang ,  Jeong-Uk Han ,  Sung-Woo Park ,  Seung-Beom Yoon ,  Ji-Hoon Park ,  Bo-Young Seo

    发明人： Sung-Taeg Kang ,  Jeong-Uk Han ,  Sung-Woo Park ,  Seung-Beom Yoon ,  Ji-Hoon Park ,  Bo-Young Seo

    IPC分类号： H01L29/788

    CPC分类号： H01L21/28273 ,  H01L21/0214 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/7881

    摘要： In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range. In addition, the size of the transistor and resulting storage cell can be minimized and the need for a high-voltage region in the circuit is mitigated, since, assuming a lowered programming voltage, pumping circuitry is not required.

    摘要翻译： 在根据该方法形成的半导体器件和半导体器件的形成方法中，在下导电层和上导电层之间设置有薄的电介质层。 在一个实施例中，薄介电层包括栅极间电介质层，下导电层包括浮动栅极，上介电层包括晶体管的控制栅极，例如非易失性存储单元晶体管。 使用导致下面的浮置栅极的表面粗糙度降低的热处理工艺形成薄介电层，并且导致在浮动栅极上形成薄的氧氮化硅层。 以这种方式，薄介电层提供在下浮动栅极和上控制栅极之间增加的电容耦合。 这也导致降低的编程电压，擦除晶体管的电压和读取电压，同时将阈值电压保持在期望的范围内。 此外，晶体管和所得到的存储单元的尺寸可以被最小化，并且减轻了对电路中的高电压区域的需要，因为假设降低的编程电压，不需要泵浦电路。

    Non-volatile memory device and method of manufacturing the same
    13.
    发明申请
    Non-volatile memory device and method of manufacturing the same 审中-公开
    非易失性存储器件及其制造方法

    公开(公告)号：US20060170034A1

    公开(公告)日：2006-08-03

    申请号：US11339741

    申请日：2006-01-25

    申请人： Sung-Woo Park ,  Sung-Taeg Kang ,  Seung-Beom Yoon ,  Yong-Tae Kim ,  Ji-Hoon Park

    发明人： Sung-Woo Park ,  Sung-Taeg Kang ,  Seung-Beom Yoon ,  Yong-Tae Kim ,  Ji-Hoon Park

    IPC分类号： H01L29/792

    CPC分类号： H01L29/66833 ,  H01L29/40117 ,  H01L29/792

    摘要： Provided are a non-volatile memory device having an improved electric characteristic and a method of manufacturing the non-volatile memory device, where the non-volatile memory device includes a substrate having a sloped portion formed therein, a first gate electrode pattern having a stacked structure in which an electric charge tunneling layer pattern, an electric charge trapping layer pattern, an electric charge shielding layer pattern, and a storage gate electrode pattern are conformably stacked on the sloped portion, a gate insulating layer pattern extending from a side of the first gate electrode pattern to the substrate, a second gate electrode pattern formed on the gate insulating layer pattern, a first junction region arranged at a side wall of the first gate electrode pattern, which does not face the second gate electrode pattern, and formed in the substrate, and a second junction region arranged at a side wall of the second gate electrode pattern, which does not face the first gate electrode pattern, and formed in the substrate.

    摘要翻译： 提供了具有改进的电特性的非易失性存储器件和制造非易失性存储器件的方法，其中非易失性存储器件包括其中形成有倾斜部分的衬底，第一栅电极图案具有堆叠 其中电荷隧道层图案，电荷捕获层图案，电荷屏蔽层图案和存储栅极电极图案顺应地堆叠在倾斜部分上的结构，从第一部分的侧面延伸的栅极绝缘层图案 栅电极图案到基板，形成在栅极绝缘层图案上的第二栅极电极图案，布置在第一栅电极图案的侧壁处的第一接合区域，其不面向第二栅电极图案，并形成在第 衬底和布置在第二栅电极图案的侧壁处的第二接合区域，其不面向顶部 t栅电极图案，并形成在基板中。

    Eeprom and methods of fabricating the same
    14.
    发明申请
    Eeprom and methods of fabricating the same 审中-公开
    Eeprom及其制造方法

    公开(公告)号：US20070018230A1

    公开(公告)日：2007-01-25

    申请号：US11490768

    申请日：2006-07-21

    申请人： Weon-Ho Park ,  Byoung-Ho Kim ,  Sang-Woo Kang ,  Jeong-Uk Han ,  Sung-Woo Park

    发明人： Weon-Ho Park ,  Byoung-Ho Kim ,  Sang-Woo Kang ,  Jeong-Uk Han ,  Sung-Woo Park

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7881 ,  H01L29/40114 ,  H01L29/42336 ,  H01L29/66825

    摘要： An EEPROM includes a tunneling opening having an inclined or a stepped sidewall. A tunnel insulation layer is formed within the tunneling opening. Using a flowed photoresist pattern as an etching mask, the gate insulator is etched to form a tunneling opening having an inclined sidewall. Thus, the tunnel insulation layer can be formed in a smaller area than an area defined by a photolithography. As a result, a width of an active region and a width of a wordline are decreased to reduce a unit cell size.

    摘要翻译： EEPROM包括具有倾斜或阶梯状侧壁的隧道开口。 在隧道开口内形成隧道绝缘层。 使用流动的光致抗蚀剂图案作为蚀刻掩模，蚀刻栅极绝缘体以形成具有倾斜侧壁的隧道开口。 因此，隧道绝缘层可以形成在比由光刻限定的区域更小的区域中。 结果，有效区域的宽度和字线的宽度减小以减小单元电池尺寸。

    METHOD AND APPARATUS FOR PRE-SCHEDULING IN CLOSED-LOOP MU-MIMO ANTENNA SYSTEM
    16.
    发明申请
    METHOD AND APPARATUS FOR PRE-SCHEDULING IN CLOSED-LOOP MU-MIMO ANTENNA SYSTEM 有权
    用于在闭环MU-MIMO天线系统中预调度的方法和装置

    公开(公告)号：US20110188599A1

    公开(公告)日：2011-08-04

    申请号：US13019366

    申请日：2011-02-02

    申请人： Seung-Won Kang ,  Sung-Woo Park ,  Soon-Young Yoon ,  Keun-Chul Hwang

    发明人： Seung-Won Kang ,  Sung-Woo Park ,  Soon-Young Yoon ,  Keun-Chul Hwang

    IPC分类号： H04B7/02

    CPC分类号： H04B7/02

    摘要： A method and an apparatus for pre-scheduling in a closed-loop multiple user multiple input multiple output (MU-MIMO) antenna system. A base station receives channel information representing a downlink channel condition of each mobile station from mobile stations in a cell, and determines a candidate user group for each of frequency bands included in an entire frequency band, based on the channel information, the candidate user group including mobile stations to which resources can be simultaneously allocated. The base station also instructs a mobile station included in each candidate user group to transmit a sounding signal through a corresponding frequency band. If the sounding signal is received through the corresponding frequency band, the base station performs a scheduling with regard to the mobile station included in each candidate user group.

    摘要翻译： 一种用于在闭环多用户多输入多输出（MU-MIMO）天线系统中进行预调度的方法和装置。 基站从小区中的移动台接收表示各移动站的下行链路信道状态的信道信息，并根据信道信息确定候选用户组，该候选用户组中包含在整个频带中的频带中的每个频带，候选用户组 包括可以同时分配资源的移动台。 基站还指示包括在每个候选用户组中的移动台通过对应的频带发送探测信号。 如果通过相应的频带接收到探测信号，则基站对每个候选用户组中包括的移动台进行调度。

    APPARATUS AND METHOD FOR DETECTING SIGNAL IN MULTI-INPUT MULTI-OUTPUT SYSTEM
    19.
    发明申请
    APPARATUS AND METHOD FOR DETECTING SIGNAL IN MULTI-INPUT MULTI-OUTPUT SYSTEM 审中-公开
    用于在多输入多输出系统中检测信号的装置和方法

    公开(公告)号：US20070291882A1

    公开(公告)日：2007-12-20

    申请号：US11762265

    申请日：2007-06-13

    申请人： Sung-Woo Park ,  Joo-Hyun Lee ,  Kyung-Joo Suh ,  Young-Hoon Kwon ,  Sung-Soo Hwang ,  Jong-In Kim ,  Joon-Hyuk Kang ,  Jong-Sub Cha

    发明人： Sung-Woo Park ,  Joo-Hyun Lee ,  Kyung-Joo Suh ,  Young-Hoon Kwon ,  Sung-Soo Hwang ,  Jong-In Kim ,  Joon-Hyuk Kang ,  Jong-Sub Cha

    IPC分类号： H04L1/02 ,  H03D1/00

    CPC分类号： H04L25/03006 ,  H04L2025/03426 ,  H04L2025/03605

    摘要： A signal detection apparatus and method using a modified stack algorithm in a Multi-Input Multi-Output (MIMO) system are provided. The signal detection method includes sorting signals received via antennas and channel coefficients for respective users in descending order, decomposing a channel matrix composed of the sorted channel coefficients into a unitary matrix and an upper-triangular matrix, determining the number of candidate symbol-sequences using the decomposed upper-triangular matrix, obtaining a signal vector for the antennas by using the sorted signals received via respective antennas and the unitary matrix, wherein the signal vector is proportional to the upper-triangular matrix, and detecting the determined number of candidate symbol-sequences by using a modified stack algorithm while expanding a stack structure for the obtained signal vector.

    摘要翻译： 提供了一种在多输入多输出（MIMO）系统中使用修改堆栈算法的信号检测装置和方法。 信号检测方法包括按照降序对各个用户的经由天线和信道系数接收的信号进行分类，将由排序的信道系数组成的信道矩阵分解成酉矩阵和上三角矩阵，使用 分解的上三角矩阵，通过使用经由各个天线接收的分类信号和单位矩阵获得天线的信号矢量，其中信号向量与上三角矩阵成比例，并且检测确定的候选符号 - 通过使用修改的堆栈算法同时扩展获得的信号向量的堆叠结构来扩展序列。

    Partial iterative detection and decoding apparatus and method in MIMO system
    20.
    发明申请
    Partial iterative detection and decoding apparatus and method in MIMO system 有权
    MIMO系统中的部分迭代检测和解码设备和方法

    公开(公告)号：US20070150797A1

    公开(公告)日：2007-06-28

    申请号：US11638785

    申请日：2006-12-14

    申请人： Keun-Chul Hwang ,  Sung-Woo Park ,  Soon-Young Yoon ,  Young-Hoon Kwon ,  June Moon

    发明人： Keun-Chul Hwang ,  Sung-Woo Park ,  Soon-Young Yoon ,  Young-Hoon Kwon ,  June Moon

    IPC分类号： H03M13/00

    CPC分类号： H04L1/005 ,  H04B7/0417 ,  H04B7/0848 ,  H04L1/0052 ,  H04L1/06

    摘要： A partial iterative detection and decoding apparatus in a Multiple Input Multiple Output (MIMO) system includes a detector for detecting signals received through at least one receive antenna to generate a first soft decision value, a decoder for decoding the first soft decision value to generate a second soft decision value, and a reliability determiner for determining a signal to be iteratively detected and decoded by using the second soft decision value. Accordingly, the complexity of the receiver is reduced and the number of iterations limited due to the complexity is increased, thereby improving the performance of the receiver.

    摘要翻译： 多输入多输出（MIMO）系统中的部分迭代检测和解码装置包括用于检测通过至少一个接收天线接收的信号以产生第一软判决值的检测器，用于解码第一软判决值以产生 第二软判决值，以及用于通过使用第二软判决值来确定要迭代检测和解码的信号的可靠性确定器。 因此，接收机的复杂度降低，并且由于复杂性而限制的迭代次数增加，从而提高了接收机的性能。