公开(公告)号：US5777369A

公开(公告)日：1998-07-07

申请号：US778264

申请日：1997-01-02

Applicant: Shi-Tron Lin ,  Ming-Tsan Yeh ,  Chau-Neng Wu ,  Chi-Hsi Wu

Inventor： Shi-Tron Lin ,  Ming-Tsan Yeh ,  Chau-Neng Wu ,  Chi-Hsi Wu

IPC: G11C11/412 ,  G11C11/419 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: G11C11/4125 ,  G11C11/419 ,  Y10S257/903

Abstract: A bit-line pull-up circuit for an SRAM device which utilizes an improved diffusion structure for enhanced immunity of the SRAM device against electrostatic discharge. The improved diffusion structure includes an undivided diffusion region that serves as a common drain for a plurality of MOS transistors. The undivided diffusion region has at least a pair of recessed diffusion edges formed on opposite sides thereof. The forming of the recessed diffusion edges prevents the so-called electrical field crowding effect and also enhances ESD immunity for the MOS transistor. Further, since the drain diffusion region is an undivided area, an increased number of metal contact windows are provided therein, and at least one of the metal contact windows is arranged substantially between the two recessed diffusion edges. In the event of an electrostatic discharge, this allows the discharge current flowing into the drain to be divided into a greater number of small-magnitude currents flowing to the source.

Abstract translation: 一种用于SRAM器件的位线上拉电路，其利用改进的扩散结构来增强SRAM器件对静电放电的免疫力。 改进的扩散结构包括用作多个MOS晶体管的公共漏极的未分开的扩散区域。 未分开的扩散区域具有形成在其相对侧上的至少一对凹进的扩散边缘。 凹陷扩散边缘的形成防止了所谓的电场拥挤效应，并且还提高了MOS晶体管的ESD抗扰度。 此外，由于漏极扩散区域是不分割的区域，所以在其中设置了增加数量的金属接触窗口，并且金属接触窗口中的至少一个基本上被布置在两个凹进的扩散边缘之间。 在静电放电的情况下，这允许流入漏极的放电电流被分成更大数量的流向源极的小电流电流。

公开(公告)号：US07075154B2

公开(公告)日：2006-07-11

申请号：US10395328

申请日：2003-03-24

Applicant: Shi-Tron Lin ,  Wei-Fan Chen

Inventor： Shi-Tron Lin ,  Wei-Fan Chen

IPC: H01L23/62

CPC classification number: H01L27/027 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge protection device formed on a substrate. The electrostatic discharge protection device includes a first isolation region formed over the substrate, an active region formed over the substrate and enclosed by the first isolation region, a second isolation region formed on the substrate and substantially surrounded by the active region, a first gate element formed in the active region, the first gate element having a first end extending over the first isolation region and a second end extending over the second isolation region, a drain region formed in the active region at a first side of the first gate element, a source region formed in the active region at a second side of the first gate element, a drain contact for electrically coupling the drain region to a first node, and a source contact for electrically coupling the source region to a second node.

公开(公告)号：US06852568B2

公开(公告)日：2005-02-08

申请号：US10281069

申请日：2002-09-16

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L23/60 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/60 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A pin-assignment method is provided for use on an IC package to arrange pin connections. The pin-assignment method can allow an improvement in the electro-static discharge (ESD) protection capability for the IC chip packed in the IC package. Specifically, the pin-assignment method organizes the no-connect pins of the IC package into groups and then assigns each of the two pins that bound each no-connect pin group to be connected to a power bus of the IC chip. This allows for an increased ESD protective capability for the no-connect pins. Moreover, the pin-assignment method can simplify the wiring complexity of the IC package.

Abstract translation: 提供了一种引脚分配方法，用于在IC封装上使用以布置引脚连接。 引脚分配方法可以改善IC封装中封装的IC芯片的静电放电（ESD）保护能力。 具体地，引脚分配方法将IC封装的无连接引脚组合成组，然后分配将要连接到IC芯片的电源总线的每个不连接引脚组的两个引脚中的每一个引脚。 这样可以提高无连接引脚的ESD保护能力。 此外，引脚分配方法可以简化IC封装的布线复杂性。

公开(公告)号：US06838708B2

公开(公告)日：2005-01-04

申请号：US10454710

申请日：2003-06-04

Applicant: Shi-Tron Lin ,  Wei-Fan Chen

Inventor： Shi-Tron Lin ,  Wei-Fan Chen

IPC: H01L27/02 ,  H01L29/74 ,  H01L31/111

CPC classification number: H01L27/0266

Abstract: An ESD protection circuit has a VDD bus, a VSS bus, an IC pad, a PMOS transistor coupled to the IC pad and the VDD bus, and an NMOS transistor coupled to the IC pad and the VSS bus. The pitch of the PMOS can smaller than the pitch of the NMOS, and the drain-contact-to-gate-spacing (DCGS) for the PMOS can be smaller than the DCGS for the NMOS.

Abstract translation: ESD保护电路具有耦合到IC焊盘和VDD总线的VDD总线，VSS总线，IC焊盘，PMOS晶体管，以及耦合到IC焊盘和VSS总线的NMOS晶体管。 PMOS的间距可以小于NMOS的间距，并且用于PMOS的漏极 - 接触 - 栅极间隔（DCGS）可以小于NMOS的DCGS。

公开(公告)号：US06611025B2

公开(公告)日：2003-08-26

申请号：US09946247

申请日：2001-09-05

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L2362

CPC classification number: H01L23/60 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A number of different arrangements of island structures are utilized for improved ESD protection. The MOSFET structure provides islands that are selectively positioned among a group of ESD protection devices for protecting the power-bus, input pins, output pins and I/O pins to achieve ESD improvement in a manner which improves overall ESD protection strength while reducing the complexity of IC simulation and modeling.

Abstract translation: 岛屿结构的许多不同布置被用于改善ESD保护。 MOSFET结构提供了选择性地定位在一组ESD保护器件中的岛，用于保护电源总线，输入引脚，输出引脚和I / O引脚，以提高整体ESD保护强度同时降低复杂性的方式实现ESD改进 的IC仿真和建模。

公开(公告)号：US06551916B2

公开(公告)日：2003-04-22

申请号：US09327875

申请日：1999-06-08

Applicant: Shi-Tron Lin ,  Chin-Jong Chan

Inventor： Shi-Tron Lin ,  Chin-Jong Chan

IPC: H01L2144

CPC classification number: H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05093 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A bond pad structure for use in wire bonding application during the packaging operation of semiconductor devices which contains a bond frame structure for holding the bond pad in place to prevent bond pad peel-off problem. The bond pad structure is a laminated structure containing a metal bond pad layer, a middle dielectric layer, and an underlying layer formed above a wafer surface. A guard band structure is formed in a spaced apart relationship from the metal bond pad layer which is connected to the underlying layer by a hole-fill. The underlying layer can be a metal layer, a semiconductor layer such as a polysilicon layer, or any material layer which has good adhesion with the hole fill material. The guard band structure exerts a downward force against the middle dielectric layer to help keeping the middle dielectric layer in place. The guard band structure also creates a localized discontinuity in the middle dielectric layer to intercept cracks that may be formed in the middle layer around the edge of the metal bond pad which is believed a main cause of bond pad peel-off problem.

Abstract translation: 一种用于在半导体器件的封装操作期间的引线接合应用中的接合焊盘结构，其包含用于将接合焊盘保持在适当位置以防止接合焊盘剥离问题的接合框架结构。 接合焊盘结构是包含形成在晶片表面上方的金属焊盘层，中间介电层和下层的层压结构。 保护带结构形成为与通过孔填充连接到下层的金属接合焊盘层间隔开的关系。 下层可以是金属层，诸如多晶硅层的半导体层，或与填充孔材料具有良好粘附性的任何材料层。 保护带结构向中间介电层施加向下的力，以帮助将中间介质层保持在适当位置。 保护带结构还在中间介电层中产生局部不连续性，以拦截可能形成在金属接合焊盘边缘周围的中间层中的裂纹，这被认为是焊盘剥离问题的主要原因。

公开(公告)号：US06388292B1

公开(公告)日：2002-05-14

申请号：US09460357

申请日：1999-12-13

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L2362

CPC classification number: H01L27/0277 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/4238 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A MOSFET structure uses angled poly-gate segments positioned between drain and source diffusion regions such that the entire continuous gate element structure is within the active region in a substrate. The gate-to-source diffusion edges are continuous along the gate body, so as to cascade the snap-back action to enhance uniform turn on of the entire gate element during an ESD event. The angled gate segments provide a total gate-to-area ratio greater than that of a multi-finger-gate configuration within an equal size active region. In addition, the gate signal RC delay is sufficient to provide noise suppression of the output voltage when the MOSFET is used as a high current-drive CMOS output buffer.

Abstract translation: MOSFET结构使用位于漏极和源极扩散区域之间的倾斜多晶硅栅极段，使得整个连续栅极元件结构在衬底中的有源区域内。 栅极到源极扩散边缘沿着栅极本体是连续的，以便在ESD事件期间级联回扣动作以增强整个栅极元件的均匀导通。 成角度的栅极段提供了大于在相等尺寸的有源区域内的多指门配置的总门限比。 此外，当MOSFET用作高电流驱动CMOS输出缓冲器时，栅极信号RC延迟足以提供输出电压的噪声抑制。

公开(公告)号：US06346900B1

公开(公告)日：2002-02-12

申请号：US09457893

申请日：1999-12-10

Applicant: Shi-Tron Lin ,  Yung-Peng Hwang

Inventor： Shi-Tron Lin ,  Yung-Peng Hwang

IPC: H03M166

CPC classification number: H03M1/682 ,  G09G3/3685 ,  G09G2310/027 ,  H03M1/765

Abstract: A driving circuit such as for driving pixels of an LCD includes first and second digital-to-analog converters respectively coupled to receive first and second digital input values. The outputs of the first and second digital-to-analog converters are connected to first and second output transistors, the outputs of which are connected together to a driving voltage output terminal. A predetermined voltage is applied to the gate of each output transistor. The first and second digital-to-analog converters and their associated output transistors correspond to upper and lower ranges of output voltage. During a display cycle, one digital-to-analog converter receives a digital value to be output as a driving voltage, while the other digital-to-analog converter receives a digital value to be output as a voltage that renders its associated output transistor nonconductive. Voltage values are selected so that the output transistors can be designed to withstand voltage values that are less than the maximum value of the full voltage range that the driving circuit can output.

Abstract translation: 诸如用于驱动LCD的像素的驱动电路包括分别耦合以接收第一和第二数字输入值的第一和第二数模转换器。 第一和第二数模转换器的输出连接到第一和第二输出晶体管，其输出端连接到驱动电压输出端。 预定的电压被施加到每个输出晶体管的栅极。 第一和第二数模转换器及其相关的输出晶体管对应于输出电压的上限和下限。 在显示周期期间，一个数模转换器接收要作为驱动电压输出的数字值，而另一个数模转换器接收要输出的数字值作为使其相关输出晶体管不导通的电压 。 选择电压值，使得输出晶体管可以设计成承受小于驱动电路可以输出的全电压范围的最大值的电压值。

公开(公告)号：US06344814B1

公开(公告)日：2002-02-05

申请号：US09458022

申请日：1999-12-10

Applicant: Shi-Tron Lin ,  Yung-Peng Hwang

Inventor： Shi-Tron Lin ,  Yung-Peng Hwang

IPC: H03M166

CPC classification number: G09G3/3685 ,  G09G2310/027 ,  G09G2310/0297

Abstract: A driving circuit suitable for driving pixels in an LCD array includes dual channel digital-to-analog converters (DACs). Each dual channel DAC outputs on channel A and channel B outputs the analog version of an applied digital signal and a non-passing voltage, respectively, and switches these outputs in response to a toggle signal. The DAC outputs are applied to paired output transistors such that one transistor of each transistor pair is rendered conductive and the other transistor is rendered non-conductive during each display cycle. By designating alternate DACs to receive upper and lower voltage range driving voltages, respectively, each pixel is alternately driven by voltages in the upper and lower voltage range and the driving voltage range applied to each pixel in one display cycle is opposite to the voltage range applied to the immediately adjacent pixels in the same display cycle.

Abstract translation: 适用于驱动LCD阵列中的像素的驱动电路包括双通道数模转换器（DAC）。 通道A和通道B上的每个双通道DAC输出分别输出所应用的数字信号和非通过电压的模拟版本，并响应于触发信号切换这些输出。 DAC输出被施加到成对的输出晶体管，使得每个晶体管对的一个晶体管被导通，并且另一个晶体管在每个显示周期期间变得不导通。 通过分别指定交替DAC来接收上限和下限电压范围驱动电压，每个像素由上下电压范围内的电压交替驱动，并且在一个显示周期内施加到每个像素的驱动电压范围与施加的电压范围相反 在相同的显示周期中到紧邻的像素。

公开(公告)号：US06246094B1

公开(公告)日：2001-06-12

申请号：US09175576

申请日：1998-10-20

Applicant: Shyh-Chyi Wong ,  Shi-Tron Lin

Inventor： Shyh-Chyi Wong ,  Shi-Tron Lin

IPC: H01L2976

CPC classification number: H01L29/66651 ,  H01L21/76224 ,  H01L21/823878

Abstract: An integrated semiconductor device includes a substrate having a buried shallow trench isolation structure and an epitaxial layer disposed over the substrate and the buried shallow trench isolation structure. The epitaxial layer includes a shallow trench isolation structure that extends over the buried shallow trench isolation structure in the substrate to substantially reduce leakage current in the substrate to prevent device latch-up.