公开(公告)号：US5882998A

公开(公告)日：1999-03-16

申请号：US55018

申请日：1998-04-03

Applicant: Harlan Lee Sur, Jr. ,  Subhas Bothra ,  Xi-Wei Lin ,  Martin H. Manley ,  Robert Payne

Inventor： Harlan Lee Sur, Jr. ,  Subhas Bothra ,  Xi-Wei Lin ,  Martin H. Manley ,  Robert Payne

IPC: H01C13/00 ,  H01L21/822 ,  H01L23/525 ,  H01L27/04 ,  H01L29/00

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.

Abstract translation: 公开了具有低功率编程阈值和抗逆向工程特性的半导体熔丝结构。 熔丝结构包括具有场氧化物区域的衬底。 具有增加的掺杂剂浓度区域的多晶硅条带位于场氧化物区域之上。 熔丝结构还包括具有位于多晶硅条上的第一和第二区域的硅化金属化层。 第一区域具有第一厚度，并且第二区域具有小于第一厚度的第二厚度，并且基本上位于多晶硅条的增加的掺杂剂浓度区域之上。 优选地，硅化金属化层的第一区域具有位于第二区域的相对侧上的第一侧和第二侧，并且所得到的熔丝结构的形状基本上是矩形。 因此，可以通过断开第二区域来编程半导体熔丝结构。

公开(公告)号：US5764563A

公开(公告)日：1998-06-09

申请号：US723007

申请日：1996-09-30

Applicant: Harlan Lee Sur, Jr. ,  Subhas Bothra

Inventor： Harlan Lee Sur, Jr. ,  Subhas Bothra

IPC: G11C11/412 ,  H01L21/02 ,  H01L27/11 ,  G11C11/00

CPC classification number: H01L28/20 ,  G11C11/412 ,  H01L27/1112

Abstract: A resistive load structure and method for making a resistive load structure for an integrated circuit includes the use of an amorphous silicon "antifuse" material. The resistive load structure can be used in an SRAM cell to provide a load to counteract charge leakage at the drains of two pull-down transistors and two pass transistors of the SRAM cell. The resistive load structure is advantageously formed by depositing an amorphous silicon pad over a conductive via, and the resistance of the resistive load structure is controlled by adjusting the thickness of the amorphous silicon pad and varying the diameter of the underlying conductive via.

Abstract translation: 用于制造用于集成电路的电阻负载结构的电阻负载结构和方法包括使用非晶硅“反熔丝”材料。 电阻负载结构可用于SRAM单元中，以提供负载以抵消SRAM单元的两个下拉晶体管和两个通过晶体管的漏极处的电荷泄漏。 有利地通过在导电通孔上沉积非晶硅垫来形成电阻负载结构，并且通过调节非晶硅垫的厚度并改变下面的导电通孔的直径来控制电阻负载结构的电阻。

公开(公告)号：US20070083833A1

公开(公告)日：2007-04-12

申请号：US11244514

申请日：2005-10-06

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

Abstract: Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known solutions where metal fill was performed after design and layout, performing metal fill during layout with a uniform pattern of conductive traces sized and spaced according to the design rules of the device to be fabricated resulting in more planning and design. Dividing the conductive traces into active and inactive segments during the design and layout identifies potentially negative impacts on critical or sensitive device elements within the device during design and layout. Previously, metal fill was implemented after design and layout and often resulted in negative impacts not previously accounted for during IC design. Embodiments of the present invention reduce degradation, seen in other devices where metal fill is incorporated after design and layout. Additionally, because the physical characteristics of inactive metal fill segments are considered during design and layout of the ICs.

Abstract translation: 本发明的实施例提供了一种系统和方法，用于在设计期间使用诸如位置和路线工具或布局工具的工具来实现金属填充。 与在设计和布局之后执行金属填充的现有已知解决方案不同，在布局期间，根据要制造的器件的设计规则，均匀地形成导电迹线图案并进行间隔，从而实现更多的规划和设计，进行金属填充。 在设计和布局期间，将导电迹线划分为有源和无源段可以在设计和布局期间识别器件内的关键或敏感器件元件的潜在负面影响。 以前，设计和布局后实施了金属填充，并且经常导致IC设计中以前未考虑的负面影响。 本发明的实施例减少了在设计和布局之后掺入金属填充物的其他装置中的劣化。 另外，因为在IC的设计和布局期间考虑了非活性金属填充段的物理特性。

公开(公告)号：US06717232B2

公开(公告)日：2004-04-06

申请号：US10406914

申请日：2003-04-02

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01L2900

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F41/042 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor inductor and a method for making a semiconductor inductor are provided. An oxide layer disposed over a substrate is etched to form an interconnect metallization trench within the oxide layer. The oxide layer is also etched to form a first inductor trench within the oxide layer such that the first inductor trench is defined in an inductor geometry. The oxide layer is then etched to form at least one via in the interconnect metallization trench and a second inductor trench over the first inductor trench in the oxide layer. The second inductor trench also has the inductor geometry. After the oxide layer is etched, the at least one via, the second inductor trench, the interconnect metallization trench and the first inductor trench are filled with copper. The semiconductor inductor is configured to have a low resistance and a high quality factor.

Abstract translation: 提供半导体电感器和制造半导体电感器的方法。 蚀刻设置在衬底上的氧化物层以在氧化物层内形成互连金属化沟槽。 也蚀刻氧化物层以在氧化物层内形成第一电感器沟槽，使得第一电感器沟槽以电感器几何形状限定。 然后蚀刻氧化物层以在互连金属化沟槽中形成至少一个通孔，以及在氧化物层中的第一电感器沟槽上方的第二电感器沟槽。 第二电感沟槽也具有电感器几何形状。 在蚀刻氧化物层之后，铜填充至少一个通孔，第二电感器沟槽，互连金属化沟槽和第一电感器沟槽。 半导体电感器被配置为具有低电阻和高品质因数。

公开(公告)号：US06649253B1

公开(公告)日：2003-11-18

申请号：US09523403

申请日：2000-03-10

Applicant: Subhas Bothra ,  Milind G. Weling

Inventor： Subhas Bothra ,  Milind G. Weling

IPC: H01L2500

CPC classification number: B24B37/013 ,  B24B37/042 ,  H01L21/31053 ,  Y10S438/959 ,  Y10T428/24917

Abstract: A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the step of depositing a dielectric layer over a reflectance stop layer. The reflectance stop layer is disposed above a component that is disposed on a semiconductor wafer. During a determination of the thickness of the dielectric layer using a reflected signal of light, the reflectance stop layer substantially reduces any light from reflecting off of the component. Therefore, the present invention provides a method and system that provides more accurate endpoint detection during a CMP process of semiconductor wafers. As a result of the present invention, an operator of a CMP machine knows precisely when to stop a CMP process of a semiconductor wafer. Furthermore, the present invention enables the operator of the CMP machine to know within a certain accuracy the film (e.g., dielectric layer) thickness remaining after the CMP process of the semiconductor wafer. Moreover, the present invention essentially eliminates excessive chemical mechanical polishing of the semiconductor wafer. As such, not as much dielectric material needs to be deposited on the wafer in order to compensate for excessive chemical mechanical polishing of the semiconductor wafer. Therefore, the present invention is able to reduce fabrication costs of semiconductor wafers.

Abstract translation: 使用具有优化的光学性质的膜用于化学机械抛光（CMP）端点检测的方法。 具体地，本发明的一个实施方案包括用于改进化学机械抛光终点检测的方法。 该方法包括在反射停止层上沉积介电层的步骤。 反射阻挡层设置在配置在半导体晶片上的部件的上方。 在使用光的反射信号确定介电层的厚度期间，反射率停止层基本上减少了从组件反射的任何光。 因此，本发明提供了一种在半导体晶片的CMP工艺期间提供更准确的端点检测的方法和系统。 作为本发明的结果，CMP机器的操作者精确地知道何时停止半导体晶片的CMP工艺。 此外，本发明使得CMP机器的操作者能够在半导体晶片的CMP处理之后以一定的精度了解剩余的膜（例如介电层）的厚度。 此外，本发明基本上消除了半导体晶片的过度的化学机械抛光。 因此，为了补偿半导体晶片的过度的化学机械抛光，不需要在晶片上沉积太多的介电材料。 因此，本发明能够降低半导体晶片的制造成本。

公开(公告)号：US06569757B1

公开(公告)日：2003-05-27

申请号：US09429540

申请日：1999-10-28

Applicant: Milind Weling ,  Subhas Bothra ,  Calvin Todd Gabriel ,  Michael Misheloff

Inventor： Milind Weling ,  Subhas Bothra ,  Calvin Todd Gabriel ,  Michael Misheloff

IPC: H01L214763

CPC classification number: H01L23/5225 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  Y10T29/49123 ,  H01L2924/00

Abstract: A method of forming a co-axial interconnect line in a dielectric layer is provided. The method includes defining a trench in the dielectric layer and then forming a shield metallization layer within the trench. After forming the shield metallization layer, a conformal oxide layer is deposited within the shield metallization layer. A center conductor is then formed within the conformal oxide layer. Once the center conductor is formed, a fill oxide layer is deposited over the center conductor. A cap metallization layer is then formed over the fill oxide layer and is in contact with the shield metallization layer.

Abstract translation: 提供了在电介质层中形成同轴互连线的方法。 该方法包括在电介质层中限定沟槽，然后在沟槽内形成屏蔽金属化层。 在形成屏蔽金属化层之后，在屏蔽金属化层内沉积保形氧化物层。 然后在保形氧化物层内形成中心导体。 一旦形成中心导体，就在中心导体上沉积填充氧化物层。 然后在填充氧化物层上形成帽金属化层，并与屏蔽金属化层接触。

公开(公告)号：US06472253B1

公开(公告)日：2002-10-29

申请号：US09440103

申请日：1999-11-15

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01L2182

CPC classification number: H01L23/5254 ,  H01L21/76888 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A programmable device and methods for making the programmable device are provided. The programmable device includes a link metallization line with an oxide layer defined above the link metallization line. A via hole is patterned in the oxide layer which defines a path to the link metallization line. A programming metallization line is defined over the oxide layer. The programming metallization line has an overlap portion that lies over the via hole. The overlap portion is configured to melt into the via hole to define a programming link between the link metallization line and the programming metallization line. In one example, the melting is accomplished by implementing a laser that can direct laser energy toward a desired programmable device to achieve the desired programming.

Abstract translation: 提供了一种用于制造可编程器件的可编程器件和方法。 可编程装置包括具有限定在连接金属化线上方的氧化物层的连接金属化线。 在氧化物层中图案化通孔，该通孔限定到连接金属化线的路径。 编程金属化线被限定在氧化物层上。 编程金属化线具有位于通孔上方的重叠部分。 重叠部分被配置为熔化到通孔中以限定连接金属化线和编程金属化线之间的编程连接。 在一个示例中，熔化通过实现可以将激光能量引导到期望的可编程器件以实现期望的编程来实现。

公开(公告)号：US06387720B1

公开(公告)日：2002-05-14

申请号：US09461702

申请日：1999-12-14

Applicant: Michael Misheloff ,  Subhas Bothra ,  Calvin Todd Gabriel ,  Milind Weling

Inventor： Michael Misheloff ,  Subhas Bothra ,  Calvin Todd Gabriel ,  Milind Weling

IPC: H01L2100

CPC classification number: G02B6/13 ,  G02B6/42 ,  G02B6/43 ,  G02B2006/12176

Abstract: A waveguide structure and method of making a waveguide for communicating optical signals is provided. The waveguide structure is made using standard CMOS fabrication operations and is integrated on the same chip having digital CMOS circuitry. An example method of making the waveguide includes forming a contact through a dielectric layer down to a substrate and coating sidewalls of the contact with a first metallization coating. The contact is then filled with a dielectric material. A partial waveguide structure is formed over the first metallization coating and the dielectric material of the contact. The partial waveguide structure is defined by a waveguide dielectric structure and a second metallization coating that is defined over the waveguide dielectric structure. A third metallization coating is then formed to define spacers along sides of the partial waveguide structure, the first metallization coating, the second metallization coating. The third metallization coating is configured to complete the waveguide structure that is filled with the waveguide dielectric structure. Optical signals can then be propagated through the waveguide structure and can be interfaced with other CMOS digital circuitry.

Abstract translation: 提供了一种制造用于传送光信号的波导的波导结构和方法。 波导结构使用标准CMOS制造操作制成，并集成在具有数字CMOS电路的同一芯片上。 制造波导的示例性方法包括通过电介质层形成接触到下一个衬底并且将接触的侧壁涂覆到第一金属化涂层。 然后用电介质材料填充接触。 在第一金属化涂层和触点的电介质材料上形成部分波导结构。 部分波导结构由波导介电结构和在波导介电结构上限定的第二金属化涂层限定。 然后形成第三金属化涂层以沿着部分波导结构，第一金属化涂层，第二金属化涂层的侧面限定间隔物。 第三金属化涂层被配置成完成填充有波导介质结构的波导结构。 光信号然后可以通过波导结构传播，并且可以与其他CMOS数字电路接口。

公开(公告)号：US06281585B1

公开(公告)日：2001-08-28

申请号：US09439098

申请日：1999-11-12

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01L2348

CPC classification number: H01L23/5226 ,  H01L21/7682 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A high speed interconnect structure and methods for making the structure are provided. The interconnect structure includes a first metallization layer having a plurality of metallization lines and a conductive via metallization layer defined over the first metallization layer. The conductive via metallization layer is configured to define self-aligned conductive vias. A non-conformal oxide layer is defined over the first metallization layer and the conductive via metallization layer such that air gaps are positioned between the plurality of metallization lines. A cap oxide layer is then defined over the non-conformal oxide. In this example, a CMP operation can be performed to expose the top surfaces of the conductive vias before a next metallization layer is defined. It should be noted that air gaps are defined without the problems associated with conductive via misalignment.

Abstract translation: 提供了一种高速互连结构和用于制造该结构的方法。 互连结构包括具有多个金属化线的第一金属化层和限定在第一金属化层上的导电通孔金属化层。 导电通孔金属化层被配置为限定自对准导电通孔。 在第一金属化层和导电通孔金属化层上限定非共形氧化物层，使得气隙位于多个金属化线之间。 然后在非共形氧化物上限定帽氧化物层。 在该示例中，可以执行CMP操作以在定义下一个金属化层之前露出导电通孔的顶表面。 应当注意，气隙被限定，而没有与导电通孔未对准相关的问题。

公开(公告)号：US06261939B1

公开(公告)日：2001-07-17

申请号：US09472384

申请日：1999-12-23

Applicant: Stephen L. Skala ,  Subhas Bothra ,  Emmanuel Demuizon

Inventor： Stephen L. Skala ,  Subhas Bothra ,  Emmanuel Demuizon

IPC: H01L2144

CPC classification number: H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/29099

Abstract: Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a photoresist mask is patterned over the metal layer. The metal layer is etched and the portion of the metal layer not masked with the photoresist is removed. In this manner, additional metal can be formed on the pad site using only one additional mask step, and the thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.

Abstract translation: 金属接合焊盘以可靠和成本有效的方式在半导体芯片中的有源电路上形成。 根据本发明的示例性实施例，在半导体芯片中的电路上形成金属焊盘。 在电路和金属接合焊盘上形成金属层，并且在金属层上图案化光致抗蚀剂掩模。 金属层被蚀刻并且金属层的未被光致抗蚀剂掩蔽的部分被去除。 以这种方式，可以仅使用一个额外的掩模步骤在焊盘位置上形成额外的金属，并且通过在随后的引线接合工艺中提供用于焊盘处的金属衬垫的垫片位置处的较厚金属来提高芯片的可靠性。