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公开(公告)号:US11508585B2
公开(公告)日:2022-11-22
申请号:US16902180
申请日:2020-06-15
Inventor: Ji Cui , Fu-Ming Huang , Ting-Kui Chang , Tang-Kuei Chang , Chun-Chieh Lin , Wei-Wei Liang , Liang-Guang Chen , Kei-Wei Chen , Hung Yen , Ting-Hsun Chang , Chi-Hsiang Shen , Li-Chieh Wu , Chi-Jen Liu
IPC: H01L21/321 , C09G1/02 , B24B37/10 , B24B37/04
Abstract: A method for CMP includes following operations. A dielectric structure is received. The dielectric structure includes a metal layer stack formed therein. The metal layer stack includes at least a first metal layer and a second metal layer, and the first metal layer and the second metal layer are exposed through a surface of the dielectric structure. A first composition is provided to remove a portion of the first metal layer from the surface of the dielectric structure. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed from the second metal layer. A CMP operation is performed to remove a portion of the second metal layer. In some embodiments, the protecting layer protects the second metal layer during the removal of the portion of the first metal layer.
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公开(公告)号:US11322345B2
公开(公告)日:2022-05-03
申请号:US16390691
申请日:2019-04-22
Inventor: Fu-Ming Huang , Liang-Guang Chen , Ting-Kui Chang , Chun-Chieh Lin
IPC: H01L21/02 , H01L21/67 , H01L21/687 , H01L21/306 , B08B1/00 , B08B1/04 , B08B3/04
Abstract: A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.
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公开(公告)号:US11121028B2
公开(公告)日:2021-09-14
申请号:US16570325
申请日:2019-09-13
Inventor: Chun-Wei Hsu , Ling-Fu Nieh , Pinlei Edmund Chu , Chi-Jen Liu , Yi-Sheng Lin , Ting-Hsun Chang , Chia-Wei Ho , Liang-Guang Chen
IPC: H01L21/768 , H01L23/532 , H01L23/522
Abstract: Semiconductor devices and methods of forming are provided. In some embodiments the semiconductor device includes a substrate, and a dielectric layer over the substrate. A first conductive feature is included in the dielectric layer, the first conductive feature comprising a first number of material layers. A second conductive feature is included in the dielectric layer, the second conductive feature comprising a second number of material layers, where the second number is higher than the first number. A first electrical connector is included overlying the first conductive feature.
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公开(公告)号:US11024540B2
公开(公告)日:2021-06-01
申请号:US16701326
申请日:2019-12-03
Inventor: Shich-Chang Suen , Kei-Wei Chen , Liang-Guang Chen
IPC: H01L21/70 , H01L21/768 , H01L21/02 , H01L29/66 , H01L21/311 , H01L21/285 , H01L21/033 , H01L29/78 , H01L23/522 , H01L21/28 , H01L21/3105 , H01L21/8238 , H01L21/3213 , H01L21/32
Abstract: A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.
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公开(公告)号:US20200006125A1
公开(公告)日:2020-01-02
申请号:US16570325
申请日:2019-09-13
Inventor: Chun-Wei Hsu , Ling-Fu Nieh , Pinlei Edmund Chu , Chi-Jen Liu , Yi-Sheng Lin , Ting-Hsun Chang , Chia-Wei Ho , Liang-Guang Chen
IPC: H01L21/768 , H01L23/532 , H01L23/522
Abstract: Semiconductor devices and methods of forming are provided. In some embodiments the semiconductor device includes a substrate, and a dielectric layer over the substrate. A first conductive feature is included in the dielectric layer, the first conductive feature comprising a first number of material layers. A second conductive feature is included in the dielectric layer, the second conductive feature comprising a second number of material layers, where the second number is higher than the first number. A first electrical connector is included overlying the first conductive feature.
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公开(公告)号:US10515808B2
公开(公告)日:2019-12-24
申请号:US15267670
申请日:2016-09-16
Inventor: Shich-Chang Suen , Chi-Jen Liu , Ying-Liang Chuang , Li-Chieh Wu , Liang-Guang Chen , Ming-Liang Yen
Abstract: A chemical mechanical polishing (CMP) system includes an O3/DIW generator, a polishing unit, and a cleaning unit. The O3/DIW generator is configured to generate an O3/DIW solution including ozone gas (O3) dissolved in deionized water (DIW). The polishing unit includes components for buffing a surface of a semiconductor structure, and a pipeline coupled to the O3/DIW generator to receive the O3/DIW solution for the buffing. The cleaning unit is coupled to the O3/DIW generator and is configured to clean the surface of the semiconductor structure using the O3/DIW solution.
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公开(公告)号:US09917173B2
公开(公告)日:2018-03-13
申请号:US15407784
申请日:2017-01-17
Inventor: Chi-Jen Liu , Li-Chieh Wu , Liang-Guang Chen , Shich-Chang Suen
IPC: H01L21/00 , H01L29/66 , H01L21/02 , H01L21/321 , H01L21/768 , H01L21/28 , H01L29/49 , H01L29/51
CPC classification number: H01L29/66545 , H01L21/02074 , H01L21/28088 , H01L21/28123 , H01L21/3212 , H01L21/76802 , H01L21/76805 , H01L21/76829 , H01L21/76831 , H01L21/76895 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6659
Abstract: A method includes forming a dummy gate of a transistor at a surface of a wafer, removing the dummy gate, and filling a metallic material into a trench left by the removed dummy gate. A Chemical Mechanical Polish (CMP) is then performed on the metallic material, wherein a remaining portion of the metallic material forms a metal gate of the transistor. After the CMP, a treatment is performed on an exposed top surface of the metal gate using an oxidation-and-etching agent comprising chlorine and oxygen.
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公开(公告)号:US20210053180A1
公开(公告)日:2021-02-25
申请号:US16550021
申请日:2019-08-23
Inventor: Michael Yen , Kao-Feng Liao , Hsin-Ying Ho , Chun-Wen Hsiao , Sheng-Chao Chuang , Ting-Hsun Chang , Fu-Ming Huang , Chun-Chieh Lin , Peng-Chung Jangjian , Ji James Cui , Liang-Guang Chen , Chih Hung Chen , Kei-Wei Chen
IPC: B24B37/26 , B24B37/24 , B24B37/005
Abstract: A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.
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公开(公告)号:US10755934B2
公开(公告)日:2020-08-25
申请号:US16711349
申请日:2019-12-11
Inventor: Shich-Chang Suen , Chi-Jen Liu , Ying-Liang Chuang , Li-Chieh Wu , Liang-Guang Chen , Ming-Liang Yen
Abstract: A chemical mechanical polishing (CMP) system and associated semiconductor fabrication methods are disclosed herein. An exemplary method includes performing a planarization process in a polishing unit of a CMP system to planarize a surface of a material layer using a CMP slurry. The method further includes, after performing the planarization process, performing a buffing process in the polishing unit of the CMP system to buff the surface of the material layer using an ozone gas dissolved in deionized water (O3/DIW) solution. The method further includes controlling the performing of the planarization process and the performing of the buffing process, such that the CMP slurry is received by the polishing unit from a first pipeline during the planarization process and the O3/DIW solution is received by the polishing unit from a second pipeline during the buffing process.
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公开(公告)号:US10510601B2
公开(公告)日:2019-12-17
申请号:US16114932
申请日:2018-08-28
Inventor: Ling-Fu Nieh , Chun-Wei Hsu , Pinlei Edmund Chu , Chi-Jen Liu , Liang-Guang Chen , Yi-Sheng Lin
IPC: H01L21/768 , H01L29/78 , H01L21/321 , H01L21/8238 , H01L23/485 , H01L29/08 , C09G1/02
Abstract: A method of manufacturing a device includes exposing at least one of a source/drain contact plug or a gate contact plug to a metal ion source solution during a manufacturing process, wherein a constituent metal of a metal ion in the metal ion source solution and the at least one source/drain contact plug or gate contact plug is the same. If the source/drain contact plug or the gate contact plug is formed of cobalt, the metal ion source solution includes a cobalt ion source solution. If the source/drain contact plug or the gate contact plug is formed of tungsten, the metal ion source solution includes a tungsten ion source solution.
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