公开(公告)号：US10573582B2

公开(公告)日：2020-02-25

申请号：US16378171

申请日：2019-04-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajeev D. Joshi ,  Hau Nguyen ,  Anindya Poddar ,  Ken Pham

IPC: H01L23/495 ,  H01L21/48 ,  H01L25/16 ,  H01L23/00 ,  H01L23/31

Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

公开(公告)号：US20190287918A1

公开(公告)日：2019-09-19

申请号：US15920242

申请日：2018-03-13

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Kishorechand Arora ,  Anindya Poddar

IPC: H01L23/552 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

Abstract: Integrated circuit (IC) packages with shields and methods of producing the same are disclosed. A disclosed IC package includes a lead frame including a die attach pad and a plurality of leads, a die attached to the die attach pad and electrically coupled to the plurality of leads, package encapsulate covering portions of the lead frame and the die, where the package encapsulate includes an indentation at a periphery of the IC package, and where the indentation includes sidewalls. The example IC package also includes a shield in the indentation, where a surface of the shield is coplanar with a surface of the package encapsulate.

公开(公告)号：US09663357B2

公开(公告)日：2017-05-30

申请号：US14963362

申请日：2015-12-09

Applicant: Texas Instruments Incorporated

Inventor： Jie Mao ,  Hau Nguyen ,  Luu Nguyen ,  Anindya Poddar

IPC: H01L21/683 ,  B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00873 ,  B81B7/007 ,  B81B2201/0214 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0278 ,  B81B2201/0292 ,  B81B2201/047 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/00333 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0159 ,  B81C2201/0181 ,  B81C2201/0188 ,  B81C2203/0136 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3121 ,  H01L24/19 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/96 ,  H01L2924/3511

Abstract: A method for fabricating packaged semiconductor devices (100) with an open cavity (110a) in panel format; placing (process 201) on an adhesive carrier tape a panel-sized grid of metallic pieces having a flat pad (230) and symmetrically placed vertical pillars (231); attaching (process 202) semiconductor chips (101) with sensor systems face-down onto the tape; laminating (process 203) and thinning (process 204) low CTE insulating material (234) to fill gaps between chips and grid; turning over (process 205) assembly to remove tape; plasma-cleaning assembly front side, sputtering and patterning (process 206) uniform metal layer across assembly and optionally plating (process 209) metal layer to form rerouting traces and extended contact pads for assembly; laminating (process 212) insulating stiffener across panel; opening (process 213) cavities in stiffener to access the sensor system; and singulating (process 214) packaged devices by cutting metallic pieces.

公开(公告)号：US20150069572A1

公开(公告)日：2015-03-12

申请号：US14025807

申请日：2013-09-12

Applicant: Texas Instruments Incorporated

Inventor： Vijaylaxmi Khanolkar ,  Anindya Poddar ,  Randall Walberg ,  Giovanni Frattini ,  Roberto Giampiero Massolini

IPC: H01F27/28 ,  H01L49/02

CPC classification number: H01F27/2804 ,  H01F2027/2809 ,  H01F2027/2819 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L28/10 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor package is provided that has a transformer formed within a multilayer dielectric laminate substrate. The transformer has a first inductor coil formed in one or more dielectric laminate layers of the substrate, a second inductor coil formed in one or more dielectric laminate layers of the substrate, and an isolation barrier comprising two or more dielectric laminate layers of the multilayer substrate positioned between the first inductor coil and the second inductor coil. The transformer may be mounted on a lead frame along with one or more integrated circuits and molded into a packaged isolation device.

Abstract translation: 提供一种半导体封装，其具有形成在多层电介质层叠基板内的变压器。 变压器具有形成在衬底的一个或多个电介质层压层中的第一电感线圈，形成在衬底的一个或多个电介质层压层中的第二电感线圈，以及包括多层衬底的两个或多个介电层压层的隔离屏障 位于第一电感线圈和第二电感线圈之间。 变压器可以与一个或多个集成电路一起安装在引线框架上并被模制成封装的隔离装置。

公开(公告)号：US20250046684A1

公开(公告)日：2025-02-06

申请号：US18362936

申请日：2023-07-31

Applicant: Texas Instruments Incorporated

Inventor： Makoto Shibuya ,  Yasmine Yan ,  Masamitsu Matsuura ,  Anindya Poddar

IPC: H01L23/495 ,  H05K1/18

Abstract: A semiconductor package comprises an integrated circuit die covered by a mold compound to form a four-sided package with a top surface and a bottom surface. A first group of no-lead contacts are exposed on a first side and on the bottom surface of the package. A second group of no-lead contacts are exposed on a second side and on the bottom surface of the package, wherein the second side is opposite the first side. A first external lead extends from a third side of the package. A second external lead extends from a fourth side of the package opposite the third side. The first and second external leads bent to extend above the top surface of the package. The first and second external leads have a gull-wing shape or a J-shape.

公开(公告)号：US20240395731A1

公开(公告)日：2024-11-28

申请号：US18321192

申请日：2023-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Masamitsu Matsuura ,  Anindya Poddar ,  Daiki Komatsu ,  Hau Thanh Nguyen ,  Patrick Francis Thompson

IPC: H01L23/00 ,  H01L21/027 ,  H01L21/56 ,  H01L23/495

Abstract: An electronic device includes a leadframe having a die pad and leads. A die that includes an active layer is attached to the die pad. A reinforcement layer is disposed on the active layer and wire bonds are attached from the active layer of the die to the leads. A mold compound encapsulates the die, the reinforcement layer, and the wire bonds.

公开(公告)号：US12154861B2

公开(公告)日：2024-11-26

申请号：US16669666

申请日：2019-10-31

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Masamitsu Matasuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar ,  Hideaki Matsunaga

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.

公开(公告)号：US12021019B2

公开(公告)日：2024-06-25

申请号：US17515176

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Ashok Surendra Prabhu ,  Edgar Dorotyao Balidoy ,  Hau Nguyen ,  Makoto Yoshino ,  Ming Li

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H05K1/02

CPC classification number: H01L23/49861 ,  H01L21/4839 ,  H01L21/565 ,  H01L23/49844 ,  H01L24/48 ,  H05K1/0204 ,  H01L2224/48177 ,  H01L2224/48178 ,  H01L2224/48248 ,  H01L2224/48465 ,  H01L2924/1811 ,  H01L2924/182

Abstract: A described example includes: a package substrate having a die pad with a die side surface and having an opposite backside surface, having leads arranged along two opposite sides and having die pad straps extending from two opposing ends of the die pad. The leads lie in a first plane, a portion of the die pad straps lie in a second plane that is spaced from the first plane and located closer to the die pad, and the die pad lies in a third plane that is spaced from and parallel to the second plane in a direction away from the first plane. A semiconductor die is mounted to the die side surface and mold compound covers the semiconductor die, a portion of the leads, and the die side surface of the die pad, and the backside surface of the die pad exposed from the mold compound.

公开(公告)号：US12009336B2

公开(公告)日：2024-06-11

申请号：US17390823

申请日：2021-07-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahmud Halim Chowdhury ,  Amin Sijelmassi ,  Murali Kittappa ,  Anindya Poddar ,  Honglin Guo ,  Joe Adam Garcia ,  John Paul Tellkamp

IPC: H01L23/00 ,  H01H85/02 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L24/48 ,  H01H85/0241 ,  H01L24/49 ,  H01L24/85 ,  H01H2085/0283 ,  H01L23/49555 ,  H01L23/49827 ,  H01L24/73 ,  H01L2224/4801 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48455 ,  H01L2224/4846 ,  H01L2224/48479 ,  H01L2224/48499 ,  H01L2224/49111 ,  H01L2224/494 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/8534 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/2064 ,  H01L2924/2075

Abstract: In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.

公开(公告)号：US20230137762A1

公开(公告)日：2023-05-04

申请号：US17515234

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Makoto Shibuya ,  Masamitsu Matsuura ,  Kengo Aoya ,  Hideaki Matsunaga ,  Anindya Poddar

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/00

Abstract: A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.