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    Multicore Bus Architecture With Non-Blocking High Performance Transaction Credit System
    12.
    发明申请
    Multicore Bus Architecture With Non-Blocking High Performance Transaction Credit System 有权
    具有非阻塞性高性能交易信用系统的多核总线架构

    公开(公告)号：US20160124883A1

    公开(公告)日：2016-05-05

    申请号：US14530203

    申请日：2014-10-31

    Applicant: Texas Instruments Incorporated

    Inventor： David M. Thompson ,  Timothy Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Matthew D. Pierson

    IPC: G06F13/40 ,  G06F13/42 ,  G06F13/364

    CPC classification number: G06F13/404 ,  G06F13/364 ,  G06F13/42 ,  G06F13/4282 ,  H04L47/10 ,  H04L47/215 ,  H04L47/39

    Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.

    Abstract translation: 本发明是总线通信协议。 主设备存储总线信用。 主设备只有在拥有足够数量和类型的总线信用时才可以传输总线事务。 在传输时，主设备减少存储的总线信用的数量。 总线信用量对应于从设备上用于接收总线事务的资源。 如果伴随着适当的信用，从设备必须接收总线交易。 从设备为事务提供服务。 然后从设备传送信用回报。 主设备将相应的信用数量和类型添加到存储量。 从设备准备接受另一个总线事务，并且主设备被重新启用以启动总线事务。 在许多类型的交互中，根据进程的状态，总线代理可以充当主机和从机。

    OPTIONAL ACKNOWLEDGEMENT FOR OUT-OF-ORDER COHERENCE TRANSACTION COMPLETION
    13.
    发明申请
    OPTIONAL ACKNOWLEDGEMENT FOR OUT-OF-ORDER COHERENCE TRANSACTION COMPLETION 审中-公开
    用于不及格相关交易完成的可选确认

    公开(公告)号：US20150370710A1

    公开(公告)日：2015-12-24

    申请号：US14841956

    申请日：2015-09-01

    Applicant: Texas Instruments Incorporated

    Inventor： Daniel B. Wu ,  Matthew D. Pierson ,  Kai Chirca ,  Timothy D. Anderson

    IPC: G06F12/08

    CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

    Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

    Abstract translation: 为了能够有效跟踪事务，使用确认期望信号来给缓存一致互连提供一个交易是否需要连贯的所有权跟踪的提示。 该信号通知高速缓存相干互连，以便在读/写传输完成时期望来自发起主机的所有权转移确认信号。 因此，高速缓存相干互连可以在其一致性点继续跟踪事务，直到在必要时从发起主机接收到确认。

    Slot/sub-slot prefetch architecture for multiple memory requestors
    16.
    发明授权
    Slot/sub-slot prefetch architecture for multiple memory requestors 有权

    公开(公告)号：US10394718B2

    公开(公告)日：2019-08-27

    申请号：US15899138

    申请日：2018-02-19

    Applicant: Texas Instruments Incorporated

    Inventor： Kai Chirca ,  Joseph R. M. Zbiciak ,  Matthew D. Pierson

    IPC: G06F12/00 ,  G06F12/0897 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0886 ,  G06F9/38

    Abstract: A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, where each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots. Each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.

    Secure Master and Secure Guest Endpoint Security Firewall
    20.
    发明申请
    Secure Master and Secure Guest Endpoint Security Firewall 审中-公开
    安全主控和安全访客端点安全防火墙

    公开(公告)号：US20140143849A1

    公开(公告)日：2014-05-22

    申请号：US14062002

    申请日：2013-10-24

    Applicant: Texas Instruments Incorporated

    Inventor： Timothy D. Anderson ,  Joseph R. M. Zbiciak ,  Matthew D. Pierson ,  Kai Chirca

    IPC: H04L29/06

    CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    Abstract: This invention is a security firewall having a security hierarchy including: secure master (SM); secure guest (SG); and non-secure (NS). There is one secure master and n secure guests. The firewall includes one secure region for secure master and one secure region for secure guests. The SM region only allows access from the secure master and the SG region allows accesses from any secure transaction. Finally, the non-secure region can be implemented two ways. In a first option, non-secure regions may be accessed only upon non-secure transactions. In a second option, non-secure regions may be accessed any processing core. In this second option, the access is downgraded to a non-secure access if the security identity is secure master or secure guest. If the two security levels are not needed the secure master can unlock the SM region to allow any secure guest access to the SM region.

    Abstract translation: 本发明是具有安全层级的安全防火墙，包括：安全主机（SM）; 安全客人（SG）; 和非安全（NS）。 有一个安全的主人和n个安全的客人。 防火墙包括一个用于安全主控的安全区域和一个用于安全访客的安全区域。 SM区域仅允许从安全主机访问，并且SG区域允许来自任何安全事务的访问。 最后，非安全区域可以实现两种方式。 在第一个选项中，只有在非安全事务时才可以访问非安全区域。 在第二个选项中，非安全区域可以被访问任何处理核心。 在第二个选项中，如果安全身份是安全主机或安全访客，则访问权限降级到非安全访问。 如果不需要两个安全级别，则安全主机可以解锁SM区域，以允许任何安全访客访问SM区域。

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