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公开(公告)号：US20190162590A1
公开(公告)日：2019-05-30
申请号：US16191430
申请日：2018-11-14
Applicant: Texas Instruments Incorporated
Inventor： Michael Zwerg , Sudhanshu Khanna , Steven C. Bartling , Brian Elies , Krishnasawamy Nagaraj , Wei-Yan Shih
IPC: G01H11/08
Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.
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公开(公告)号：US20250094276A1
公开(公告)日：2025-03-20
申请号：US18964844
申请日：2024-12-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Michael Zwerg , Gregory North , Ashwini Gopinath
Abstract: Various examples disclosed herein relate to trimming of system elements to prepare the elements for execution of boot code and application code. In an example embodiment, a system is provided. The system includes system control circuitry, direct memory access (DMA) circuitry, and processing circuitry. The system control circuitry is configured to instruct the DMA circuitry to obtain trim data from memory upon detecting that a first group of system elements has reached an initialized state. The DMA circuitry obtains the trim data and writes it to trim registers. The system control circuitry supplies the trim data to a second group of system elements to bring them to an operational level, then instructs the processing circuitry to execute boot code.
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13.发明授权公开(公告)号：US11953969B2
公开(公告)日：2024-04-09
申请号：US17404125
申请日：2021-08-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Michael Zwerg , Steven Craig Bartling , Sudhanshu Khanna
IPC: G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F3/06 , G06F11/07
CPC classification number: G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F3/061 , G06F3/0625 , G06F3/0634 , G06F3/0655 , G06F3/0656 , G06F3/0688 , G06F11/07 , Y02D10/00 , Y02D30/50
Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.
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公开(公告)号：US11847430B2
公开(公告)日：2023-12-19
申请号：US17521019
申请日：2021-11-08
Applicant: Texas Instruments Incorporated
Inventor： Sudhanshu Khanna , Hao Meng , Michael Zwerg , Christy Leigh She , Steven Craig Bartling
CPC classification number: G06F7/62 , G06F1/26 , G06F1/30 , G08C13/02 , H03K5/24 , G11C11/56 , H03K21/40 , H03K21/403
Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.
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公开(公告)号：US20220057996A1
公开(公告)日：2022-02-24
申请号：US17521019
申请日：2021-11-08
Applicant: Texas Instruments Incorporated
Inventor： Sudhanshu Khanna , Hao Meng , Michael Zwerg , Christy Leigh She , Steven Craig Bartling
Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.
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Patent Agency Ranking
16.发明授权公开(公告)号：US10037071B2
公开(公告)日：2018-07-31
申请号：US14918133
申请日：2015-10-20
Applicant: Texas Instruments Incorporated
Inventor： Andreas Dannenberg , Brent Peterson , Aik K. Goh , Joerg Schreiner , Michael Zwerg , Steven Craig Bartling
IPC: G06F1/00 , G06F1/32 , G06F12/02 , G06F9/4401
CPC classification number: G06F1/3275 , G06F1/3243 , G06F1/3287 , G06F9/4418 , G06F12/0246 , G06F2212/7203 , Y02D10/14 , Y02D10/152 , Y02D10/171 , Y02D10/44 , Y02D50/20
Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a software routine configured to be run by the CPU that effects saving to a non-volatile memory a state of the CPU and/or the device's peripherals before entering the deep low-power mode. The software routine can be configured to control this state storage in response to detecting a low power event, i.e., loss of power sufficient to run the CPU, or a software command to enter the deep low power mode to save power as part of an efficiency program. Then, upon wake up from the deep low power mode, the software routine is first run by the CPU to effect restoring from the non-volatile memory the state of the CPU and the peripherals before execution of a primary application for the central processing unit.
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公开(公告)号：US12158804B1
公开(公告)日：2024-12-03
申请号：US18345449
申请日：2023-06-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Michael Zwerg , Gregory North , Ashwini Gopinath
Abstract: Various examples disclosed herein relate to trimming of system elements to prepare the elements for execution of boot code and application code. In an example embodiment, a system is provided. The system includes system control circuitry, direct memory access (DMA) circuitry, and processing circuitry. The system control circuitry is configured to instruct the DMA circuitry to obtain trim data from memory upon detecting that a first group of system elements has reached an initialized state. The DMA circuitry obtains the trim data and writes it to trim registers. The system control circuitry supplies the trim data to a second group of system elements to bring them to an operational level, then instructs the processing circuitry to execute boot code.
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公开(公告)号：US12072229B2
公开(公告)日：2024-08-27
申请号：US17462090
申请日：2021-08-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Michael Zwerg , Sudhanshu Khanna , Steven C. Bartling , Brian Elies , Krishnasawamy Nagaraj , Wei-Yan Shih
IPC: G01H11/08
CPC classification number: G01H11/08
Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.
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公开(公告)号：US20210389174A1
公开(公告)日：2021-12-16
申请号：US17462090
申请日：2021-08-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Michael Zwerg , Sudhanshu Khanna , Steven C. Bartling , Brian Elies , Krishnasawamy Nagaraj , Wei-Yan Shih
IPC: G01H11/08
Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.
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公开(公告)号：US11200030B2
公开(公告)日：2021-12-14
申请号：US16711042
申请日：2019-12-11
Applicant: Texas Instruments Incorporated
Inventor： Sudhanshu Khanna , Hao Meng , Michael Zwerg , Christy Leigh She , Steven Craig Bartling
Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.
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