中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

55 records (took 0.056 seconds)

    AREA EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDED MEMORIES
    12.
    发明申请
    AREA EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDED MEMORIES 审中-公开

    公开(公告)号：US20170157524A1

    公开(公告)日：2017-06-08

    申请号：US15434717

    申请日：2017-02-16

    Applicant: Texas Instruments Incorporated

    Inventor： Prakash Narayanan ,  Nikita Naresh ,  Vaskar Sarkar ,  Rajat Mehrotra

    IPC: G11C29/00

    CPC classification number: G11C29/12 ,  G11C29/38 ,  G11C29/40 ,  G11C2029/0401 ,  G11C2029/2602

    Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.

    COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROCESSES, CIRCUITS, DEVICES AND SYSTEMS
    13.
    发明申请
    COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROCESSES, CIRCUITS, DEVICES AND SYSTEMS 审中-公开
    内部链观察，过程，电路，设备和系统的压缩扫描链诊断

    公开(公告)号：US20150006987A1

    公开(公告)日：2015-01-01

    申请号：US14487538

    申请日：2014-09-16

    Applicant: Texas Instruments Incorporated

    Inventor： Prakash Narayanan ,  Arvind Jain ,  Sundarrajan Subramanian ,  Rubin A. Parekhji

    IPC: G01R31/3185

    CPC classification number: G01R31/3177 ,  G01R31/318536 ,  G01R31/318547

    Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

    Abstract translation: 电子扫描电路包括解压缩器（510），由解压缩器（510）馈送的多个扫描链（520.i），耦合到多个扫描链（520.i）以扫描的扫描电路（502,504） 由扫描链（520.i）馈送的掩蔽电路（590）和耦合到屏蔽电路（590）的可扫描屏蔽鉴定电路（550,560,580），屏蔽鉴定电路（550） ，560,580）以及扫描链（520.i）的扫描以及可扫描掩蔽鉴定电路（550,560,580）可扫描由解压缩器（510）的位的扫描，以及可扫描掩蔽鉴定电路（550,560,580） 通过屏蔽电路扫描扫描链（590）后扫描位。 还公开了其它扫描电路，处理，电路，装置和系统。

    AREA EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDDED MEMORIES
    19.
    发明申请
    AREA EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDDED MEMORIES 审中-公开

    公开(公告)号：US20180174663A1

    公开(公告)日：2018-06-21

    申请号：US15896817

    申请日：2018-02-14

    Applicant: Texas Instruments Incorporated

    Inventor： Prakash Narayanan ,  Nikita Naresh ,  Vaskar Sarkar ,  Rajat Mehrotra

    IPC: G11C29/12

    CPC classification number: G11C29/12 ,  G11C29/38 ,  G11C29/40 ,  G11C2029/0401 ,  G11C2029/2602

    Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.

    Area efficient parallel test data path for embedded memories
    20.
    发明授权
    Area efficient parallel test data path for embedded memories 有权

    公开(公告)号：US09899103B2

    公开(公告)日：2018-02-20

    申请号：US15434717

    申请日：2017-02-16

    Applicant: Texas Instruments Incorporated

    Inventor： Prakash Narayanan ,  Nikita Naresh ,  Vaskar Sarkar ,  Rajat Mehrotra

    IPC: G11C7/00 ,  G11C29/12

    CPC classification number: G11C29/12 ,  G11C29/38 ,  G11C29/40 ,  G11C2029/0401 ,  G11C2029/2602

    Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.

Patent Agency Ranking