公开(公告)号：US20140164856A1

公开(公告)日：2014-06-12

申请号：US13709247

申请日：2012-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raguram Damodaran ,  Naveen Bhoria ,  Aman Kokrady

IPC: G11C29/12

CPC classification number: G11C29/16 ,  G11C11/41 ,  G11C2029/0401

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. Test data comparison is performed in a distributed data logging architecture to minimize the number of interconnections between the distributed data loggers and the pBIST.

Abstract translation: 用于测试嵌入式存储器的可编程内置自测（pBIST）系统，其中被测存储器被并入未与pBIST模块集成的多个子芯片中。 在分布式数据记录架构中执行测试数据比较，以最小化分布式数据记录器和pBIST之间的互连数量。

公开(公告)号：US20140164844A1

公开(公告)日：2014-06-12

申请号：US13709220

申请日：2012-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raguram Damodaran ,  Naveen Bhoria ,  Aman Kokrady

IPC: G06F11/27

CPC classification number: G06F11/27 ,  G11C29/16 ,  G11C29/32 ,  G11C2029/0401

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. A distributed Data Logger is incorporated into each sub chip, communicating with the pBIST over serial and a compressed parallel data paths.

Abstract translation: 用于测试嵌入式存储器的可编程内置自测（pBIST）系统，其中被测存储器被并入未与pBIST模块集成的多个子芯片中。 分布式数据记录器被并入到每个子芯片中，通过串行和压缩的并行数据路径与pBIST进行通信。

公开(公告)号：US20140108737A1

公开(公告)日：2014-04-17

申请号：US13649269

申请日：2012-10-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Raguram Damodaran ,  Abhijeet Ashok Chachad

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0891 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/1021 ,  G06F2212/62 ,  Y02D10/13

Abstract: A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. A range check is performed on each CPU access while a block invalidate operation is in progress, and an access that maps to within the address range of the block invalidate operation will be trated as a cache miss to ensure that the requesting CPU will receive valid data.

Abstract translation: 通过将块无效操作与正常CPU访问重叠来消除多CPU环境中的块无效操作的延迟的方法，从而使得延迟变得透明。 在块无效操作正在进行时，对每个CPU访问执行范围检查，并且映射到块无效操作的地址范围内的访问将被作为高速缓存未命中，以确保请求的CPU将接收到有效的数据 。

公开(公告)号：US09268708B2

公开(公告)日：2016-02-23

申请号：US14637580

申请日：2015-03-04

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Abhijeet Ashok Chachad ,  Jonathan (Son) Hung Tran ,  David Matthew Thompson

IPC: G06F12/12 ,  G06F12/10 ,  G06F7/483 ,  G06F9/30 ,  H03M13/35 ,  H03M13/29 ,  G06F11/10 ,  G06F13/16 ,  G06F13/18 ,  H03K19/00 ,  G06F1/32 ,  H03K21/00 ,  G06F12/02 ,  G06F12/08 ,  G06F13/364

CPC classification number: G06F12/1081 ,  G06F1/3296 ,  G06F7/483 ,  G06F9/3012 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/1605 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/18 ,  G06F13/364 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/221 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/608 ,  H03K19/0016 ,  H03K21/00 ,  H03M13/2903 ,  H03M13/353 ,  Y02D10/124 ,  Y02D10/172 ,  Y02D50/20

Abstract: This invention assures cache coherence in a multi-level cache system upon eviction of a higher level cache line. A victim buffer stored data on evicted lines. On a DMA access that may be cached in the higher level cache the lower level cache sends a snoop write. The address of this snoop write is compared with the victim buffer. On a hit in the victim buffer the write completes in the victim buffer. When the victim data passes to the next cache level it is written into a second victim buffer to be retired when the data is committed to cache. DMA write addresses are compared to addresses in this second victim buffer. On a match the write takes place in the second victim buffer. On a failure to match the controller sends a snoop write.

公开(公告)号：US20160026569A1

公开(公告)日：2016-01-28

申请号：US14875801

申请日：2015-10-06

Applicant: Texas Instruments Incorporated

Inventor： Naveen Bhoria ,  Raguram Damodaran ,  Abhijeet Ashok Chachad

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0891 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/1021 ,  G06F2212/62 ,  Y02D10/13

Abstract: A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. A range check is performed on each CPU access while a block invalidate operation is in progress, and an access that maps to within the address range of the block invalidate operation will be treated as a cache miss to ensure that the requesting CPU will receive valid data.

Abstract translation: 通过将块无效操作与正常CPU访问重叠来消除多CPU环境中的块无效操作的延迟的方法，从而使得延迟变得透明。 在块无效操作正在进行时，对每个CPU访问执行范围检查，并且映射到块无效操作的地址范围内的访问将被视为缓存未命中，以确保请求的CPU将接收有效数据 。

公开(公告)号：US20150178221A1

公开(公告)日：2015-06-25

申请号：US14637580

申请日：2015-03-04

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Abhijeet Ashok Chachad ,  Jonathan (Son) Hung Tran ,  David Matthew Thompson

IPC: G06F12/12

CPC classification number: G06F12/1081 ,  G06F1/3296 ,  G06F7/483 ,  G06F9/3012 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/1605 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/18 ,  G06F13/364 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/221 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/608 ,  H03K19/0016 ,  H03K21/00 ,  H03M13/2903 ,  H03M13/353 ,  Y02D10/124 ,  Y02D10/172 ,  Y02D50/20

Abstract: This invention assures cache coherence in a multi-level cache system upon eviction of a higher level cache line. A victim buffer stored data on evicted lines. On a DMA access that may be cached in the higher level cache the lower level cache sends a snoop write. The address of this snoop write is compared with the victim buffer. On a hit in the victim buffer the write completes in the victim buffer. When the victim data passes to the next cache level it is written into a second victim buffer to be retired when the data is committed to cache. DMA write addresses are compared to addresses in this second victim buffer. On a match the write takes place in the second victim buffer. On a failure to match the controller sends a snoop write.

Abstract translation: 本发明在驱逐较高级别的高速缓存行时确保多级高速缓存系统中的高速缓存一致性。 受害者缓冲区将数据存储在被驱逐的行上。 在可能缓存在较高级别缓存中的DMA访问中，下级缓存发送窥探写。 将该窥探写的地址与受害缓冲区进行比较。 在受害缓冲区中的命中，写入在受害缓冲区中完成。 当受害者数据传递到下一个缓存级别时，当数据被提交到高速缓存时，它被写入第二个受害缓冲区以便退出。 DMA写地址与第二个受害缓冲区中的地址进行比较。 在匹配中，写入发生在第二个受害缓冲区中。 在无法匹配的情况下，控制器发出一个窥探写。

公开(公告)号：US20130243148A1

公开(公告)日：2013-09-19

申请号：US13888050

申请日：2013-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ramakrishnan Venkatasubramanian ,  Anthony Lell ,  Raguram Damodaran

IPC: H03K21/00

CPC classification number: G06F12/1081 ,  G06F1/3296 ,  G06F7/483 ,  G06F9/3012 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/1605 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/18 ,  G06F13/364 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/221 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/608 ,  H03K19/0016 ,  H03K21/00 ,  H03M13/2903 ,  H03M13/353 ,  Y02D10/124 ,  Y02D10/172 ,  Y02D50/20

Abstract: A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. One period of an output clock signal is synthesized in response to each assertion of the count indicator when the fractional indicator indicates the divide ratio is N.5. One period of the output clock signal is synthesized in response to two assertions of the count indicator when the fractional indicator indicates the divide ratio is an integer.

Abstract translation: 提供了一个时钟分频器，其配置为将高速输入时钟信号除以奇数，偶数或分数分频比。 例如，输入时钟可以具有1GHz或更高的时钟周期频率。 输入时钟信号被分割以产生输出时钟信号，首先接收表示分频比N的除法因子值F，其中N可以是奇数或偶数整数。 分数指示符表示分数指示符为1时的分频比为N.5，当分数指示符为零时表示分频比为N。 对于分数除数，F被设置为2（N.5）/ 2，并且对于整数分频比，F被设置为N / 2。 当N为偶数时，每N / 2个输入时钟周期，计数指示器被置位。 当N为奇数时，计数指示灯交替显示N / 2个输入时钟周期，然后1 + N / 2个输入时钟周期。 当分数指示符表示分频比为N.5时，响应于计数指示符的每个断言，合成输出时钟信号的一个周期。 当分数指示符表示分频比是整数时，响应于计数指示符的两个断言，合成输出时钟信号的一个周期。

公开(公告)号：US20230244611A1

公开(公告)日：2023-08-03

申请号：US18083703

申请日：2022-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  Raguram Damodaran ,  Ramakrishnan Venkatasubramanian ,  Joseph Raymond Michael Zbiciak

IPC: G06F12/1081 ,  G06F7/483 ,  G06F9/30 ,  H03M13/35 ,  H03M13/29 ,  G06F11/10 ,  G06F13/16 ,  G06F13/18 ,  H03K19/00 ,  G06F1/3296 ,  H03K21/00 ,  G06F12/02 ,  G06F12/12 ,  G06F12/0811 ,  G06F12/0815

CPC classification number: G06F12/1081 ,  G06F7/483 ,  G06F9/3012 ,  H03M13/353 ,  H03M13/2903 ,  G06F11/1064 ,  G06F13/1605 ,  G06F13/18 ,  H03K19/0016 ,  G06F1/3296 ,  H03K21/00 ,  G06F12/0246 ,  G06F12/12 ,  G06F12/0811 ,  G06F12/0815 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/364

Abstract: A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

公开(公告)号：US10713180B2

公开(公告)日：2020-07-14

申请号：US15991241

申请日：2018-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  Raguram Damodaran ,  Ramakrishnan Venkatasubramanian ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F12/1081 ,  G06F7/483 ,  H03M13/35 ,  H03M13/29 ,  G06F11/10 ,  G06F13/16 ,  G06F13/18 ,  H03K19/00 ,  G06F1/3296 ,  H03K21/00 ,  G06F12/02 ,  G06F12/12 ,  G06F12/0811 ,  G06F12/0815 ,  G06F13/364

Abstract: A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

公开(公告)号：US20180129608A9

公开(公告)日：2018-05-10

申请号：US14874842

申请日：2015-10-05

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Joseph Raymond Michael Zbiciak ,  Naveen Bhoria

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0888 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F2212/1021 ,  G06F2212/6022 ,  G06F2212/70

Abstract: The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.