公开(公告)号：US20170123548A1

公开(公告)日：2017-05-04

申请号：US14926265

申请日：2015-10-29

Applicant: Texas Instruments Incorporated

Inventor： Wei-Yan Shih ,  Steve Kummerl ,  Mark Stephen Toth ,  Alok Lohia ,  Terry Lee Sculley ,  Seung Bae Lee ,  Scott Robert Summerfelt

IPC: G06F3/041

CPC classification number: G06F3/0414 ,  G06F3/0416

Abstract: An integrated force sensing element includes a piezoelectric sensor formed in an integrated circuit (IC) chip and a strain gauge at least partially overlying the piezoelectric sensor, where the piezoelectric sensor is able to flex. A human-machine interface using the integrated force sensing element is also disclosed and may include a conditioning circuit, temperature gauge, FRAM and a processor core.

公开(公告)号：US11815526B2

公开(公告)日：2023-11-14

申请号：US17732475

申请日：2022-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Scott Robert Summerfelt ,  Benjamin Stassen Cook

IPC: G01P21/00 ,  G01P15/09

CPC classification number: G01P21/00 ,  G01P15/09

Abstract: A method includes measuring a temperature of a semiconductor die, in which the semiconductor die includes a piezoelectric device, a pyroelectric device, and a memory. The method further includes receiving a first signal from the pyroelectric device, and based on the first signal, determining a parameter to be combined with a second signal from the piezoelectric device. The method further includes storing the parameter and the measured temperature into the memory.

公开(公告)号：US20220148912A1

公开(公告)日：2022-05-12

申请号：US17583322

申请日：2022-01-25

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  Thomas Dyer Bonifield ,  Sreeram Subramanyam Nasum ,  Peter Smeys ,  Benjamin Stassen Cook

IPC: H01L21/762 ,  H01L49/02 ,  H01L27/12 ,  H01L23/544 ,  H01L23/00 ,  H01L21/78

Abstract: In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.

公开(公告)号：US11049980B2

公开(公告)日：2021-06-29

申请号：US16668004

申请日：2019-10-30

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  Benjamin Stassen Cook

IPC: H01L29/88 ,  H01L29/66 ,  H01L23/522

Abstract: In an integrated circuit, a metal-insulator-metal (MIM) diode includes: a first metallization structure level having a first metal layer; a first dielectric layer over the first metal layer; a metal contact or via on the first metal layer and extending through a portion of the first dielectric layer; and a second metallization structure level having a second metal layer; and a second dielectric layer over the second metal layer. The diode has a first electrode on the metal contact or via, a multilayer dielectric structure on the first electrode, and a second electrode between the multilayer dielectric structure and the second metal layer.

公开(公告)号：US20210183915A1

公开(公告)日：2021-06-17

申请号：US16716652

申请日：2019-12-17

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  Hassan Omar Ali ,  Benjamin Stassen Cook

IPC: H01L27/146

Abstract: In described examples an integrated circuit (IC) has multiple layers of dielectric material overlying at least a portion of a surface of a substrate. A trench is etched through the layers of dielectric material to expose a portion the substrate to form a trench floor, the trench being surrounded by a trench wall formed by the layers of dielectric material. A metal perimeter band surrounds the trench adjacent the trench wall, the perimeter band being embedded in one of the layers of the dielectric material.

公开(公告)号：US20190051812A1

公开(公告)日：2019-02-14

申请号：US15671252

申请日：2017-08-08

Applicant: Texas Instruments Incorporated

Inventor： Wei-Yan Shih ,  Sudhanshu Khanna ,  Michael Zwerg ,  Juergen Luebbe ,  Gregory Allen North ,  Steven C. Bartling ,  Leah Trautmann ,  Scott Robert Summerfelt

IPC: H01L41/107 ,  B06B1/06 ,  H01L41/04 ,  H01L41/047

Abstract: A piezoelectric sensor with: (i) a capacitive element, comprising piezoelectric material; (ii) a pre-conditioning circuit, comprising circuitry for establishing a polarization of the capacitive element in a polarizing mode; and (iii) signal amplification circuitry for providing a piezoelectric-responsive output signal, in response to charge across the capacitive element in a sensing mode.

公开(公告)号：US20180374861A1

公开(公告)日：2018-12-27

申请号：US16056827

申请日：2018-08-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Huang-Chun Wen ,  Richard Allen Bailey ,  Antonio Guillemo Acosta ,  John A. Rodriguez ,  Scott Robert Summerfelt ,  Kemal Tamer San

IPC: H01L27/11507 ,  H01L21/02 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

公开(公告)号：US20160086960A1

公开(公告)日：2016-03-24

申请号：US14728683

申请日：2015-06-02

Applicant: Texas Instruments Incorporated

Inventor： Huang-Chun Wen ,  Richard Allen Bailey ,  Antonio Guillermo Acosta ,  John A. Rodriguez ,  Scott Robert Summerfelt ,  Kemal Tamer San

IPC: H01L27/115 ,  H01L21/02 ,  H01L29/78 ,  H01L23/31 ,  H01L23/29 ,  H01L21/326 ,  H01L23/00

CPC classification number: H01L27/11507 ,  H01L21/02118 ,  H01L21/0217 ,  H01L21/02197 ,  H01L21/02318 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/07025 ,  H01L2924/014

Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

Abstract translation: 固化施加到铁电集成电路的表面的钝化层，以增强铁电结构的极化特性。 在制造有源器件之后，将钝化层（例如聚酰亚胺）施加到铁电集成电路的表面。 钝化层通过暴露于低于铁电材料的居里温度的高温固化，持续时间短，例如十分钟左右。 可以使用变频微波能量来实现这种固化。 固化的钝化层达到拉伸应力状态，结果赋予了下伏的铁电材料的压应力。 在固化过程之前极化铁电材料可以进一步提高极化。

公开(公告)号：US20150221516A1

公开(公告)日：2015-08-06

申请号：US14682944

申请日：2015-04-09

Applicant: Texas Instruments Incorporated

Inventor： Mark Robert Visokay ,  Scott Robert Summerfelt

IPC: H01L21/285 ,  H01L21/3213 ,  C23C14/08 ,  C22C32/00 ,  B22F3/10 ,  B22F5/00 ,  C22C28/00 ,  H01L49/02 ,  C23C14/34

CPC classification number: H01L21/2855 ,  B22F3/10 ,  B22F5/00 ,  C22C28/00 ,  C22C32/001 ,  C22C32/0015 ,  C22C32/0031 ,  C22C32/0042 ,  C23C14/08 ,  C23C14/082 ,  C23C14/3414 ,  H01L21/32133 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/75

Abstract: A sputtering target for a conductive oxide, such as SrRuO3, to be used for the sputter deposition of a conductive film that is to be in contact with a ferroelectric material in an integrated circuit. The sputtering target is formed by the sintering of a powder mixture of the conductive oxide with a sintering agent of an oxide of one of the constituents of the ferroelectric material. For the example of lead-zirconium-titanate (PZT) as the ferroelectric material, the sintering agent is one or more of a lead oxide, a zirconium oxide, and a titanium oxide. The resulting sputtering target is of higher density and lower porosity, resulting in an improved sputter deposited film that does not include an atomic species beyond those of the ferroelectric material deposited adjacent to that film.

Abstract translation: 用于导电氧化物的溅射靶，例如SrRuO 3，用于在集成电路中与铁电材料接触的导电膜的溅射沉积。 溅射靶是通过将导电氧化物的粉末混合物与铁电体材料的组分之一的氧化物的烧结剂烧结而形成的。 作为铁电材料的钛酸锆酸铅（PZT）的例子，烧结剂是氧化铅，氧化锆，氧化钛中的一种以上。 所得到的溅射靶具有更高的密度和更低的孔隙率，导致改进的溅射沉积膜不包括超过与该膜相邻沉积的铁电材料的原子种类的原子种类。

公开(公告)号：US20140131781A1

公开(公告)日：2014-05-15

申请号：US14158948

申请日：2014-01-20

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  Hasibur Rahman ,  John Paul Campbell

IPC: H01L23/528 ,  H01L27/06

CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76843 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5256 ,  H01L23/5283 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.

Abstract translation: 集成电路在衬底中包含较低的组件，PMD层，PMD层上的上部组件，PMD层中的下部触点将一些上部组件连接到某些较低组件，上部组件上的ILD层，ILD上的金属互连线 层和上部触点，其将一些上部部件连接到某些金属互连线，并且还包括与上部环形触点对准的下部环形触点的环形堆叠触点。 下触点和上接触件都具有衬垫上的金属衬垫和接触金属。 下环形触头具有至少一个衬垫金属环和围绕PMD材料柱的接触金属，并且上触点具有至少一个衬垫金属环和围绕ILD材料柱的接触金属。 环形堆叠的触点将金属互连件连接到下部组件。