公开(公告)号：US20230154974A1

公开(公告)日：2023-05-18

申请号：US17529750

申请日：2021-11-18

Applicant: Texas Instruments Incorporated

Inventor： Elizabeth Costner Stewart ,  Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams

IPC: H01L49/02 ,  H01L23/00 ,  H01L25/16 ,  H01L23/495

CPC classification number: H01L28/60 ,  H01L24/05 ,  H01L25/16 ,  H01L23/49575 ,  H01L2224/0556 ,  H01L2224/05624

Abstract: An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.

公开(公告)号：US11495553B2

公开(公告)日：2022-11-08

申请号：US16526765

申请日：2019-07-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams

IPC: H01L23/64 ,  H01L27/07 ,  H01L23/00 ,  H01L49/02 ,  B81B7/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/495

Abstract: A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

公开(公告)号：US20220189873A1

公开(公告)日：2022-06-16

申请号：US17120123

申请日：2020-12-12

Applicant: Texas Instruments Incorporated

Inventor： Klaas De Haan ,  Mikhail Valeryevich Ivanov ,  Tobias Bernhard Fritz ,  Swaminathan Sankaran ,  Thomas Dyer Bonifield

IPC: H01L23/522 ,  H01L23/50 ,  H04L25/02 ,  H01L21/50

Abstract: An electronic device has a substrate and first and second metallization levels with a resonant circuit. The first metallization level has a first dielectric layer on a side of the substrate, and a first metal layer on the first dielectric layer. The second metallization level has a second dielectric layer on the first dielectric layer and the first metal layer, and a second metal layer on the second dielectric layer. The electronic device includes a first plate in the first metal layer, and a second plate spaced apart from the first plate in the second metal layer to form a capacitor. The electronic device includes a winding in one of the first and second metal layers and coupled to one of the first and second plates in a resonant circuit.

公开(公告)号：US20220069066A1

公开(公告)日：2022-03-03

申请号：US17007726

申请日：2020-08-31

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams ,  Elizabeth Costner Stewart

IPC: H01L49/02 ,  H01L23/522 ,  H01L27/02

Abstract: A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.

公开(公告)号：US20200161225A1

公开(公告)日：2020-05-21

申请号：US16751088

申请日：2020-01-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anindya Poddar ,  Thomas Dyer Bonifield ,  Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/532

Abstract: Described herein is a technology or a method for fabricating a flip-chip on lead (FOL) semiconductor package. A lead frame includes an edge on surface that has a geometric shape that provides a radial and uniform distribution of electric fields. By placing the formed geometric shape along an active die of a semiconductor chip, the electric fields that are present in between the lead frame and the semiconductor chip are uniformly concentrated.

公开(公告)号：US08890223B1

公开(公告)日：2014-11-18

申请号：US13960344

申请日：2013-08-06

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Byron Williams ,  Shrinivasan Jaganathan

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L29/00 ,  H01L49/02 ,  H01L27/02

CPC classification number: H01L28/60 ,  H01G4/10 ,  H01G4/14 ,  H01G4/206 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/06 ,  H01L27/0288 ,  H01L28/40 ,  H01L29/0642 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/0603 ,  H01L2224/48463 ,  H01L2924/13091 ,  H01L2924/00

Abstract: An integrated circuit includes isolation capacitors which include a silicon dioxide dielectric layer and a polymer dielectric layer over the layer of silicon dioxide. The silicon dioxide dielectric layer and the polymer dielectric layer extend across the integrated circuit. Top plates of the isolation capacitors have bond pads for wire bonds or bump bonds. Bottom plates of the isolation capacitors are connected to components of the integrated circuit. Other bond pads are connected to components in the integrated circuit through vias through the silicon dioxide dielectric layer and the polymer dielectric layer.

Abstract translation: 集成电路包括隔离电容器，其包括在二氧化硅层上的二氧化硅介电层和聚合物电介质层。 二氧化硅介电层和聚合物电介质层跨过集成电路延伸。 隔离电容器的顶板具有用于引线键合或凸起键的接合焊盘。 隔离电容器的底板连接到集成电路的组件。 其他接合焊盘通过通孔通过二氧化硅介电层和聚合物电介质层连接到集成电路中的组件。

公开(公告)号：US20240112953A1

公开(公告)日：2024-04-04

申请号：US18148231

申请日：2022-12-29

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Elizabeth Costner Stewart ,  Thomas Dyer Bonifield ,  Byron Lovell Williams ,  Kashyap Barot ,  Viresh Chinchansure ,  Sreeram N S

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528

Abstract: A microelectronic device including a galvanic isolator with filler metal within an upper isolation element. The galvanic isolator includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The upper isolation element contains tines of filler metal which are electrically tied to each other and are electrically tied to the upper isolation element. The ends of the tines are rounded to minimize electric fields. The filler metal increases the overall metal density on the metal layer of the upper isolation element to meet the typical metal density requirements of modern microelectronic fabrication processing.

公开(公告)号：US11942402B2

公开(公告)日：2024-03-26

申请号：US17679065

申请日：2022-02-23

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065 ,  H01L49/02

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L23/642 ,  H01L24/45 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/50 ,  H01L28/40

Abstract: An isolator device includes a laminate die having a dielectric laminate material with a metal laminate layer on one side of the dielectric laminate material, the metal laminate layer being a patterned layer providing at least a first plate, including a dielectric layer over the first plate that includes an aperture exposing a portion of the first plate. An integrated circuit (IC) including a substrate having a semiconductor surface includes circuitry including a transmitter and/or a receiver, the IC including a top metal layer providing at least a second plate coupled to a node in the circuitry, with at least one passivation layer on the top metal layer. A non-conductive die attach (NCDA) material for attaching a side of the dielectric laminate material is opposite the metal laminate layer to the IC so that the first plate is at least partially over the second plate to provide a capacitor.

公开(公告)号：US11881449B2

公开(公告)日：2024-01-23

申请号：US16916748

申请日：2020-06-30

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas Dyer Bonifield

IPC: H01L23/522 ,  H01L23/58 ,  H01L23/64 ,  H01L27/01

CPC classification number: H01L23/5223 ,  H01L23/5227 ,  H01L23/585

Abstract: An integrated circuit includes a semiconductor substrate and a plurality of dielectric layers over the semiconductor substrate, including a top dielectric layer. A metal plate or metal coil is located over the top dielectric layer; a metal ring is located over the top dielectric layer and substantially surrounds the metal plate or metal coil. A protective overcoat overlies the metal ring and overlies the metal plate or metal coil. A trench opening is formed through the protective overcoat, with the trench opening exposing the top dielectric layer between the metal plate/coil and the metal ring, the trench opening substantially surrounding the metal plate or metal coil.

公开(公告)号：US20230197634A1

公开(公告)日：2023-06-22

申请号：US17558017

申请日：2021-12-21

Applicant: Texas Instruments Incorporated

Inventor： Elizabeth Costner Stewart ,  Jeffrey Alan West ,  Thomas Dyer Bonifield

IPC: H01L23/00 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/585 ,  H01L28/10

Abstract: An integrated circuit with a first conductive region, a second conductive region, a plurality of dielectric layers of a first material type between the first conductive region and the second conductive region, and at least one dielectric layer of a second material type, between a first dielectric layer in the plurality of dielectric layers of a first material type and a second dielectric layer in the plurality of dielectric layers of the first material type. Each dielectric layer of a first material type has a thickness in a range from 0.5 μm to 5.0 μm, and the at least one dielectric layer of a second material type is not contacting a metal and has a thickness less than 2.0 μm, and the second material type differs from the first material type in at least one of compression stress or elements in the first material type as compared to elements in the second material type.