公开(公告)号：US20240387696A1

公开(公告)日：2024-11-21

申请号：US18785670

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/768

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

公开(公告)号：US20240387249A1

公开(公告)日：2024-11-21

申请号：US18785934

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/762 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line in a direction parallel to a backside surface of the first dielectric layer.

公开(公告)号：US12107131B2

公开(公告)日：2024-10-01

申请号：US18328520

申请日：2023-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes a first interconnect structure and multiple channel layers stacked over the first interconnect structure. A bottommost one of the multiple channel layers is thinner than rest of the multiple channel layers. The semiconductor device further includes a gate stack wrapping around each of the channel layers except a bottommost one of the channel layers; a source/drain feature adjoining the channel layers; a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature; and a dielectric feature under the bottommost one of the channel layers and directly contacting the first conductive via.

公开(公告)号：US12094942B2

公开(公告)日：2024-09-17

申请号：US17815089

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/285 ,  H01L21/321 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/535 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/28568 ,  H01L21/3212 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/535 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a metal gate structure (MG) formed over a substrate, a first gate spacer formed on a first sidewall of the MG, a second gate spacer formed on a second sidewall of the MG opposite to the first sidewall, where the second gate spacer is shorter than the first gate spacer, a source/drain (S/D) contact (MD) adjacent to the MG, where a sidewall of the MD is defined by the second gate spacer, and a contact feature configured to electrically connect the MG to the MD.

公开(公告)号：US20240304687A1

公开(公告)日：2024-09-12

申请号：US18232986

申请日：2023-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Ning Yao ,  Chia-Hao Chang ,  Shih-Cheng Chen ,  Chih-Hao Wang ,  Chia-Cheng Tsai ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin ,  Jung-Hung Chang ,  Tsung-Han Chuang

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41775 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/775

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a polysilicon structure on a substrate, depositing a first spacer layer on the polysilicon structure, depositing a second spacer layer on the first spacer layer, forming a S/D region on the substrate, removing the second spacer layer, depositing a third spacer layer on the first spacer layer and on the S/D region, depositing an ESL on the third spacer layer, depositing an ILD layer on the etch stop layer, and replacing the polysilicon structure with a gate structure surrounding the nanostructured layer.

公开(公告)号：US12080776B2

公开(公告)日：2024-09-03

申请号：US17463370

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei Jhan ,  Kuan-Ting Pan ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: A device includes a substrate and a fin isolation structure between a first gate structure and a second gate structure. The first gate structure wraps around a first vertical stack of nanostructure channels overlying a first fin. The second gate structure wraps around a second vertical stack of nanostructure channels overlying a second fin. The fin isolation structure extends from an upper surface of the first gate structure to an upper surface of the substrate. A trench isolation structure is between the first fin and the fin isolation structure, and has different etch selectivity than the fin isolation structure.

公开(公告)号：US12080646B2

公开(公告)日：2024-09-03

申请号：US18446113

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L23/5283 ,  H01L21/76883 ,  H01L21/76892 ,  H01L29/401 ,  H01L29/41775 ,  H01L21/76885

Abstract: A method having a semiconductor substrate received and a first dielectric layer is formed over the semiconductor substrate. A trench is formed in the first dielectric layer. The trench is filled to form a conductive layer in the first dielectric layer. The conductive layer is segmented to form a first conductive feature and a second conductive feature separated from each other by a recess. The recess is filled with a second dielectric layer, such that one or both of the conductive features are end-capped by a portion of the first dielectric layer and a portion of the second dielectric layer.

公开(公告)号：US12074167B2

公开(公告)日：2024-08-27

申请号：US18053236

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L29/04 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/66545 ,  H01L21/30625 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/045 ,  H01L29/165 ,  H01L29/7848

Abstract: A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.

公开(公告)号：US12074164B2

公开(公告)日：2024-08-27

申请号：US17815185

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Yi-Ruei Jhan ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: According to one example, a method includes forming a first set of fin structures on a substrate, forming a sacrificial material between fin structures within the first set of fin structures, forming a dummy gate with a planar bottom surface over the fin structures and the sacrificial material, forming sidewall structures on the dummy gate, laterally etching the sacrificial material underneath the sidewall structures, depositing a lower sidewall structure where the sacrificial material was removed, removing the dummy gate, removing the sacrificial material, and forming a real gate over the fin structures.

公开(公告)号：US12051738B2

公开(公告)日：2024-07-30

申请号：US17666241

申请日：2022-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan You ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Li-Yang Chuang

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/165

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region.