公开(公告)号：US10672870B2

公开(公告)日：2020-06-02

申请号：US16036302

申请日：2018-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Lung Chen ,  Kang-Min Kuo ,  Long-Jie Hong

IPC: H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/167 ,  H01L29/165 ,  H01L29/36 ,  H01L21/033

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure has a channel region and a source/drain region. A gate structure is formed over the channel region of the fin structure. A first source/drain etching is performed to recess the source/drain region of the fin structure. After the first source/drain etching, a second source/drain etching is performed to further recess the source/drain region of the fin structure. After the second source/drain etching, a third source/drain etching is performed to further recess the source/drain region of the fin structure, thereby forming a source/drain recess. One or more epitaxial layers are formed in the source/drain recess. The first source/drain etching is isotropic etching and the second source/drain etching is anisotropic etching.

公开(公告)号：US20200111719A1

公开(公告)日：2020-04-09

申请号：US16705469

申请日：2019-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/31 ,  H01L21/768 ,  H01L23/29 ,  H01L23/48 ,  H01L23/482 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L29/40 ,  H01L29/41

Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

公开(公告)号：US10522543B2

公开(公告)日：2019-12-31

申请号：US16055526

申请日：2018-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo ,  Cheng-Wei Lian

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/40 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

Abstract: Methods for forming a semiconductor structure are provided. The method includes forming a first dummy gate structure and forming first spacers over a sidewall of the first dummy gate structure. The method includes removing the first dummy gate structure to form a first trench between the first spacers and forming a first capping layer in the first trench. A first portion of the first capping layer covers a sidewall of the first trench and a second portion of the first capping layer covers a bottom surface of the first trench. The method further includes oxidizing a sidewall of the first portion of the first capping layer and a top surface of the second portion of the first capping layer to form a first capping oxide layer and forming a first work function metal layer and forming a first gate electrode layer over the first work function metal layer.

公开(公告)号：US10475699B2

公开(公告)日：2019-11-12

申请号：US15888999

申请日：2018-02-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jia Hsieh ,  Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/768 ,  H01L29/16 ,  H01L29/161 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78 ,  H01L23/485 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/165 ,  H01L23/532

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

公开(公告)号：US20190115273A1

公开(公告)日：2019-04-18

申请号：US16218842

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/31 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L23/532 ,  H01L23/528 ,  H01L23/29 ,  H01L29/41 ,  H01L29/40 ,  H01L23/522 ,  H01L23/482

CPC classification number: H01L23/3171 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/564 ,  H01L29/401 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

公开(公告)号：US09887129B2

公开(公告)日：2018-02-06

申请号：US14477689

申请日：2014-09-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jia Hsieh ,  Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/94 ,  H01L21/768 ,  H01L29/16 ,  H01L29/161 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78 ,  H01L23/485 ,  H01L21/8238 ,  H01L21/311 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/31105 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76855 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

公开(公告)号：US20160247741A1

公开(公告)日：2016-08-25

申请号：US15146012

申请日：2016-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/31 ,  H01L23/532 ,  H01L23/29 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/3171 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/564 ,  H01L29/401 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is disclosed in some embodiments. The device includes a substrate, and a layer disposed over the substrate. The layer includes an opening extending through the layer. A plurality of bar or pillar structures or a tapered region are arranged in a peripheral portion of the opening and laterally surround a central portion of the opening. A metal body extends through the central portion of the opening.

Abstract translation: 在一些实施例中公开了一种半导体器件。 该器件包括衬底和设置在衬底上的层。 该层包括延伸穿过该层的开口。 多个杆或柱结构或锥形区域布置在开口的周边部分中并横向围绕开口的中心部分。 金属体延伸穿过开口的中心部分。

公开(公告)号：US09076804B2

公开(公告)日：2015-07-07

申请号：US13974400

申请日：2013-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/485 ,  H01L21/4763 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/522 ,  H01L23/528 ,  H01L29/40

CPC classification number: H01L23/3171 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/564 ,  H01L29/401 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having enhanced passivation integrity is disclosed. The device includes a substrate, a first layer, and a metal layer. The first layer is formed over the substrate. The first layer includes a via opening and a tapered portion proximate to the via opening. The metal layer is formed over the via opening and the tapered portion of the first layer. The metal layer is substantially free from gaps and voids.

Abstract translation: 公开了一种具有增强的钝化完整性的半导体器件。 该器件包括衬底，第一层和金属层。 第一层形成在衬底上。 第一层包括通孔开口和靠近通孔开口的锥形部分。 金属层形成在通孔开口和第一层的锥形部分之上。 金属层基本上没有间隙和空隙。

公开(公告)号：US20140353833A1

公开(公告)日：2014-12-04

申请号：US13905438

申请日：2013-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ming Peng ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L29/7843 ,  H01L21/82345 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/5226 ,  H01L23/562 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) stress compensation layers that reduce stress on one or more underlying semiconductor devices, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices. A stressed element is located within a back-end-of-the-line stack at a position overlying the one or more semiconductor devices. A stressing layer is located over the stressed element induces a stress upon the stressed element. A stress compensation layer, located over the stressed element, provides a counter-stress to reduce the stress induced on the stressed element by the stressing layer. By reducing the stress induced on the stressed element, stress on the semiconductor substrate is reduced, improving uniformity of performance of the one or more semiconductor devices.

Abstract translation: 本公开涉及具有一个或多个后端（BEOL）应力补偿层的集成芯片，其减小一个或多个下层半导体器件上的应力，以及相关联的形成方法。 在一些实施例中，集成芯片具有带有一个或多个半导体器件的半导体衬底。 应力元件位于覆盖一个或多个半导体器件的位置处的后端行堆叠中。 应力层位于应力元件上方会对应力元件产生应力。 位于应力元件上方的应力补偿层提供反应力，以减轻应力层对受应力元件的应力。 通过减少在应力元件上产生的应力，减小半导体衬底上的应力，提高一个或多个半导体器件的性能的均匀性。

公开(公告)号：US11101344B2

公开(公告)日：2021-08-24

申请号：US16595100

申请日：2019-10-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.