中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

19 records (took 0.019 seconds)

    MIXED COMPLEMENTARY FIELD EFFECT AND UNIPOLAR TRANSISTORS AND METHODS OF FORMING THE SAME
    11.
    发明申请
    MIXED COMPLEMENTARY FIELD EFFECT AND UNIPOLAR TRANSISTORS AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20250113596A1

    公开(公告)日：2025-04-03

    申请号：US18375593

    申请日：2023-10-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jui-Chien Huang ,  Cheng-Yin Wang ,  Wei-Cheng Lin ,  Kao-Cheng Lin ,  Szuya Liao

    IPC: H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

    Abstract: Embodiments include mixed complementary field effect and unipolar transistors and methods of forming the same. In an embodiment, a structure includes: a first semiconductor nanostructure; a second semiconductor nanostructure; a first isolation structure interposed between the first semiconductor nanostructure and the second semiconductor nanostructure; a first source/drain region extending laterally from an end of the first semiconductor nanostructure, the first source/drain region having a first conductivity type; a second source/drain region extending laterally from an end of the second semiconductor nanostructure, the second source/drain region having the first conductivity type, the second source/drain region aligned vertically with the first source/drain region; and a first gate structure surrounding the first semiconductor nanostructure and the second semiconductor nanostructure.

    Three dimensional cross-access dual-port bit cell design
    16.
    发明授权
    Three dimensional cross-access dual-port bit cell design 有权
    三维交叉访问双端口位单元设计

    公开(公告)号：US09275710B2

    公开(公告)日：2016-03-01

    申请号：US14014431

    申请日：2013-08-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei Min Chan ,  Kao-Cheng Lin ,  Yen-Huei Chen

    IPC: G11C8/16 ,  G11C11/41 ,  G11C8/14 ,  G11C8/08 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  G11C5/06

    CPC classification number: G11C8/16 ,  G11C5/06 ,  G11C5/063 ,  G11C8/08 ,  G11C8/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417

    Abstract: A semiconductor memory comprises a dual-port memory array having a plurality of cross-access dual-port bit cells arranged in a plurality of rows and a plurality of columns, wherein each of the plurality of cross-access dual-port bit cells has two cross-access ports for read and write of one or more bits of data to the cross-access dual port bit cell. The semiconductor memory further comprises a pair of word lines associated with at least one of the plurality of rows of the dual-port memory array, wherein the pair of word lines is configured to carry a pair of row selection signals for enabling one or more read and write operations on one or more cross-access dual-port bit cells in the row. The semiconductor memory further comprises a pair of column selection lines associated with at least one of the plurality of columns of the dual port memory array, wherein the pair of column selection lines is configured to carry a pair of column selection signals for enabling the cross-access dual-port bit cells in the column during the read and write operations.

    Abstract translation: 半导体存储器包括双端口存储器阵列，其具有以多行和多列布置的多个交叉访问双端口位单元，其中多个交叉访问双端口位单元中的每一个具有两个 交叉访问端口用于读取和写入一个或多个位数据到交叉访问双端口位单元。 半导体存储器还包括与双端口存储器阵列的多行中的至少一个相关联的一对字线，其中该对字线被配置为携带一对行选择信号，以使一个或多个读取 并对行中的一个或多个交叉访问双端口位单元进行写入操作。 半导体存储器还包括与双端口存储器阵列的多个列中的至少一个相关联的一对列选择线，其中该列选择线被配置为承载一对列选择信号， 在读取和写入操作期间访问列中的双端口位单元。

    Dual port SRAM with dummy read recovery
    19.
    发明授权
    Dual port SRAM with dummy read recovery 有权
    具有虚拟读取恢复功能的双端口SRAM

    公开(公告)号：US09129707B2

    公开(公告)日：2015-09-08

    申请号：US14043869

    申请日：2013-10-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kao-Cheng Lin ,  Wei Min Chan ,  Yen-Huei Chen

    IPC: G11C8/16 ,  G11C11/419 ,  G11C7/10 ,  G11C11/412

    CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412

    Abstract: An integrated includes a dual port memory cell such as a SRAM cell. A first port dummy read recovery block couples the first port complementary bit line to a high voltage supply node during a write logic low operation to the data node through the second port bit line, and couples the first port bit line to a high voltage supply node during a write logic low operation to the complementary data node through the second port complementary bit line. A second port dummy read recovery block couples the second port complementary bit line to a high voltage supply node during a write logic low operation to the data node through the first port bit line, and couples the second port bit line to a high voltage supply node during a write logic low operation to the complementary data node through the first port complementary bit line.

    Abstract translation: 集成的包括诸如SRAM单元的双端口存储单元。 第一端口虚拟读取恢复块在写入逻辑低操作期间通过第二端口位线将第一端口互补位线耦合到高电压供应节点到数据节点，并且将第一端口位线耦合到高电压供应节点 在通过第二端口互补位线到互补数据节点的写入逻辑低操作期间。 第二端口虚拟读恢复块在写逻辑低操作期间通过第一端口位线将第二端口互补位线耦合到高电压电源节点，并将第二端口位线耦合到高电压电源节点 在通过第一端口互补位线到互补数据节点的写入逻辑低操作期间。

Patent Agency Ranking