公开(公告)号：US10957559B2

公开(公告)日：2021-03-23

申请号：US16575698

申请日：2019-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/36 ,  H01L23/373 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

Abstract: A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip.

公开(公告)号：US20210028145A1

公开(公告)日：2021-01-28

申请号：US16518992

申请日：2019-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/367

Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes a plurality of integrated circuits, a first encapsulant, a first redistribution structure, a plurality of conductive pillars, a second redistribution structure, a second encapsulant and a third redistribution structure. The first encapsulant encapsulates the integrated circuits. The first redistribution structure is disposed over the first encapsulant and electrically connected to the integrated circuits. The conductive pillars are disposed over the first redistribution structure. The conductive pillars are disposed between and electrically connected to the first and second redistribution structures. The second encapsulant encapsulates the conductive pillars and is disposed between the first redistribution structure and second redistribution structure. The third redistribution structure is disposed over and electrically connected to the second redistribution structure, wherein a linewidth of the third redistribution structure is larger than a linewidth of the second redistribution structure.

公开(公告)号：US20200294916A1

公开(公告)日：2020-09-17

申请号：US16354105

申请日：2019-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Chi-Hui Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Kuo-Chung Yee ,  Chen-Hua Yu

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes semiconductor dies, an encapsulant and a redistribution structure. The semiconductor dies are disposed side by side. Each semiconductor die has an active surface, a backside surface, and an inner side surface connecting the active surface and the backside surface. The encapsulant wraps the semiconductor dies and exposes the active surfaces of the semiconductor dies. The redistribution structure is disposed on the encapsulant and the active surfaces of the semiconductor dies. The inner side surfaces of most adjacent semiconductor dies face each other. The redistribution structure establishes single-ended connections between most adjacent semiconductor dies by crossing over the facing inner side surfaces of the most adjacent semiconductor dies.

公开(公告)号：US10748825B2

公开(公告)日：2020-08-18

申请号：US16382542

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/31 ,  H01L23/48 ,  H01L21/50 ,  H01L31/0232 ,  H01L31/09 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L31/0203 ,  H01L33/52 ,  H01L33/48 ,  H01L23/28 ,  H01L23/485 ,  H01L23/00 ,  H01L27/146 ,  H01L33/54 ,  H01L21/311 ,  H01L21/683 ,  H01L21/768 ,  H01L23/29 ,  H01L25/16 ,  H01L25/00

Abstract: In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad disposed over a first substrate and a second conductive pad disposed over a second substrate. The second conductive pad is a multi-layer structure having an uppermost metal layer including titanium or nickel. A molding structure surrounds the first substrate and the second substrate. A conductive structure is over the first substrate and the second substrate. The conductive structure is conductively coupled to the second conductive pad.

公开(公告)号：US20200066642A1

公开(公告)日：2020-02-27

申请号：US16671188

申请日：2019-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/367 ,  H01L25/065

Abstract: An integrated fan-out package includes an integrated circuit, a plurality of semiconductor devices, a first redistribution circuit structure, and an insulating encapsulation. The integrated circuit has an active surface and a rear surface opposite to the active surface. The semiconductor devices are electrically connected the integrated circuit. The first redistribution circuit structure is disposed between the integrated circuit and the semiconductor devices. The first redistribution circuit structure is electrically connected to the integrated circuit and the semiconductor devices respectively. The first redistribution circuit structure has a first surface, a second surface opposite to the first surface, and lateral sides between the first surface and the second surface. The insulating encapsulation encapsulates the integrated circuit and the semiconductor devices and covers the first surface and the second surface of the first redistribution circuit structure. Furthermore, methods for fabricating the integrated fan-out package are also provided.

公开(公告)号：US20200043838A1

公开(公告)日：2020-02-06

申请号：US16600752

申请日：2019-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/498 ,  H01L23/373 ,  H01L23/433 ,  H01L21/48

Abstract: Some embodiments relate to a semiconductor package. The package includes a substrate having an upper surface and a lower surface. A first chip is disposed over a first portion of the upper surface of the substrate. A second chip is disposed over a second portion of the upper surface of the substrate. A first plurality of carbon nano material pillars are disposed over an uppermost surface of the first chip, and a second plurality of carbon nano material pillars are disposed over an uppermost surface of the second chip. A molding compound is disposed above the substrate, and encapsulates the first chip, the first plurality of carbon nano material pillars, the second chip, and the second plurality of carbon nano material pillars.

公开(公告)号：US20190139925A1

公开(公告)日：2019-05-09

申请号：US15854736

申请日：2017-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Chun-Hui Yu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L23/538 ,  H01L21/683 ,  H01L21/56 ,  H01L21/768 ,  H01L21/3105 ,  H01L25/00

Abstract: A package structure includes an insulating encapsulation, at least one first chip, a redistribution layer and a bonding layer. The at least one first chip is encapsulated in the insulating encapsulation. The redistribution layer is located on the insulating encapsulation and the at least one first chip and electrically connected to the at least one first chip. The bonding layer mechanically connects the redistribution layer and the at least one first chip.

公开(公告)号：US10283473B1

公开(公告)日：2019-05-07

申请号：US15854736

申请日：2017-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Chun-Hui Yu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L23/538 ,  H01L21/683 ,  H01L21/56 ,  H01L21/768 ,  H01L21/3105 ,  H01L25/00 ,  H01L21/66

Abstract: A package structure includes an insulating encapsulation, at least one first chip, a redistribution layer and a bonding layer. The at least one first chip is encapsulated in the insulating encapsulation. The redistribution layer is located on the insulating encapsulation and the at least one first chip and electrically connected to the at least one first chip. The bonding layer mechanically connects the redistribution layer and the at least one first chip.

公开(公告)号：US20190051604A1

公开(公告)日：2019-02-14

申请号：US15676958

申请日：2017-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L23/367 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/1434 ,  H01L2924/1531 ,  H01L2924/351 ,  H01L2224/83 ,  H01L2224/81

Abstract: An integrated fan-out package includes an integrated circuit, a plurality of semiconductor devices, a first redistribution circuit structure, and an insulating encapsulation. The integrated circuit has an active surface and a rear surface opposite to the active surface. The semiconductor devices are electrically connected the integrated circuit. The first redistribution circuit structure is disposed between the integrated circuit and the semiconductor devices. The first redistribution circuit structure is electrically connected to the integrated circuit and the semiconductor devices respectively. The first redistribution circuit structure has a first surface, a second surface opposite to the first surface, and lateral sides between the first surface and the second surface. The insulating encapsulation encapsulates the integrated circuit and the semiconductor devices and covers the first surface and the second surface of the first redistribution circuit structure. Furthermore, methods for fabricating the integrated fan-out package are also provided.

公开(公告)号：US20180247912A1

公开(公告)日：2018-08-30

申请号：US15966426

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/00 ,  H01L23/42 ,  H01L23/373

CPC classification number: H01L24/29 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/4334 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/00014

Abstract: A method of forming a semiconductor package includes attaching a thermal conductivity layer to a chip. The chip has a first surface and a second surface. The thermal conductivity layer is attached to the first surface of the chip. The thermal conductivity layer provides a path through which heat generated from the chip is dissipated to the ambient. A substrate is attached to the second surface of the chip after attaching the thermal conductivity layer to the chip. A molding compound is formed to encapsulate the chip and the thermal conductivity layer.