公开(公告)号：US20240379618A1

公开(公告)日：2024-11-14

申请号：US18782561

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/48 ,  H01L23/544

Abstract: A package includes a first semiconductor substrate; an integrated circuit die bonded to the first semiconductor substrate with a dielectric-to-dielectric bond; a molding compound over the first semiconductor substrate and around the integrated circuit die; and a redistribution structure over the first semiconductor substrate and the integrated circuit die, wherein the redistribution structure is electrically connected to the integrated circuit die. The integrated circuit die includes a second semiconductor substrate, and wherein the second semiconductor substrate comprises a first sidewall, a second sidewall, and a third sidewall opposite the first sidewall and the second sidewall, and the second sidewall is offset from the first sidewall.

公开(公告)号：US12119318B2

公开(公告)日：2024-10-15

申请号：US18303302

申请日：2023-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L23/00 ,  H01L21/18 ,  H01L21/768 ,  H01L23/373 ,  H01L23/48 ,  H01L23/532 ,  H01L33/00

CPC classification number: H01L24/09 ,  H01L21/187 ,  H01L21/76807 ,  H01L21/76871 ,  H01L23/481 ,  H01L23/53238 ,  H01L24/03 ,  H01L23/3735 ,  H01L33/0093 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2924/01013

Abstract: A device includes an interconnect structure over a substrate, multiple first conductive pads over and connected to the interconnect structure, a planarization stop layer extending over the sidewalls and top surfaces of the first conductive pads of the multiple first conductive pads, a surface dielectric layer extending over the planarization stop layer, and multiple first bonding pads within the surface dielectric layer and connected to the multiple first conductive pads.

公开(公告)号：US12113005B2

公开(公告)日：2024-10-08

申请号：US18186525

申请日：2023-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/80895 ,  H01L2225/06544 ,  H01L2924/0695

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming an insulation layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device to the insulation layer and a portion of the plurality of bond pads through hybrid bonding.

公开(公告)号：US12087668B2

公开(公告)日：2024-09-10

申请号：US18194792

申请日：2023-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/02311 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/08146

Abstract: A semiconductor device includes a first passivation layer over a circuit and. conductive pad over the first passivation layer, wherein the conductive pad is electrically connected to the circuit. A second passivation layer is disposed over the conductive pad and the first passivation layer, and has a first opening and a second opening. The first opening exposes an upper surface of a layer that extends underneath the conductive pad, and the second opening exposes the conductive pad. A first insulating layer is disposed over the second passivation layer and filling the first and second openings. A through substrate via extends through the insulating layer, second passivation layer, passivation layer, and substrate. A side of the through substrate via and the second passivation layer have a gap that is filled with the first insulating layer. A conductive via extends through the first insulating layer and connecting to the conductive pad.

公开(公告)号：US12009386B2

公开(公告)日：2024-06-11

申请号：US17872701

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ying-Ju Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L23/522 ,  H01G4/30 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01G4/30 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5223 ,  H01L23/5226

Abstract: Methods of forming a super high density metal-insulator-metal (SHDMIM) capacitor and semiconductor device are disclosed herein. A method includes depositing a first insulating layer over a semiconductor substrate and a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates. A first set of contact plugs through the series of conductive layers contacts one or more conductive layers of a first portion of the series of conductive layers. A second set of contact plugs through the series of dielectric layers avoids contact of a second portion of the series of conductive layers, the second portion of the series of conductive layers electrically floating.

公开(公告)号：US11942436B2

公开(公告)日：2024-03-26

申请号：US17883932

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ying-Ju Chen ,  Ming-Fa Chen

IPC: H01L23/00 ,  H01L21/74 ,  H01L21/78 ,  H01L23/31 ,  H01L23/525 ,  H01L23/544 ,  H01L23/58

CPC classification number: H01L23/544 ,  H01L21/74 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/525 ,  H01L23/562 ,  H01L23/585

Abstract: A method of forming a semiconductor device includes: forming first electrical components in a substrate in a first device region of the semiconductor device; forming a first interconnect structure over and electrically coupled to the first electrical components; forming a first passivation layer over the first interconnect structure, the first passivation layer extending from the first device region to a scribe line region adjacent to the first device region; after forming the first passivation layer, removing the first passivation layer from the scribe line region while keeping a remaining portion of the first passivation layer in the first device region; and dicing along the scribe line region after removing the first passivation layer.

公开(公告)号：US11935802B2

公开(公告)日：2024-03-19

申请号：US17808632

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L23/28 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/28 ,  H01L23/367 ,  H01L25/0657 ,  H01L25/50

Abstract: A package and a method of forming the same are provided. The package includes: a die stack bonded to a carrier, the die stack including a first integrated circuit die, the first integrated circuit die being a farthest integrated circuit die of the die stack from the carrier, a front side of the first integrated circuit die facing the carrier; a die structure bonded to the die stack, the die structure including a second integrated circuit die, a backside of the first integrated circuit die being in physical contact with a backside of the second integrated circuit die, the backside of the first integrated circuit die being opposite the front side of the first integrated circuit die; a heat dissipation structure bonded to the die structure adjacent the die stack; and an encapsulant extending along sidewalls of the die stack and sidewalls of the heat dissipation structure.

公开(公告)号：US20240021583A1

公开(公告)日：2024-01-18

申请号：US18362098

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/80896 ,  H01L2225/06582 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2225/06541

Abstract: Packages and methods of fabricating the same are provided. The package includes a first die, wherein the first die includes a plurality of through vias from a first surface of the first die toward a second surface of the first die; a second die disposed below the first die, wherein the second surface of the first die is bonded to the second die; an isolation layer disposed in the first die, wherein the plurality of through vias extend through the isolation layer; an encapsulation laterally surrounding the first die, wherein the encapsulation is laterally separated from the isolation layer; a buffer layer disposed over the first die, the isolation layer, and the encapsulation; and a plurality of conductive terminals disposed over the isolation layer, wherein the plurality of conductive terminals is electrically connected to corresponding ones of the plurality of through vias.

公开(公告)号：US20240014095A1

公开(公告)日：2024-01-11

申请号：US17859297

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen

IPC: H01L23/367 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/3677 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/08 ,  H01L25/0657 ,  H01L24/80 ,  H01L21/4882 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06517 ,  H01L2924/182 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/08145 ,  H01L2224/08245 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor package including a thermally conductive bridge and a method of forming are provided. The semiconductor package may include a first semiconductor device having a first substrate and first contact pads on the first substrate, a first thermally conductive feature on the first substrate and extending into the first substrate, a second semiconductor device over the first substrate, wherein the second semiconductor device may include second contact pads electrically connected to the first contact pads, a first thermally conductive bridge over the first semiconductor device and beside the second semiconductor device, and a first encapsulant over the first semiconductor device and along sidewalls of the second semiconductor device and the first thermally conductive bridge. The first thermally conductive bridge may include a second substrate and a second thermally conductive feature on the second substrate and extending into the second substrate, wherein the second thermally conductive feature may be bonded to the first thermally conductive feature.

公开(公告)号：US11862599B2

公开(公告)日：2024-01-02

申请号：US17325667

申请日：2021-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ying-Ju Chen ,  Ming-Fa Chen

IPC: H01L23/544 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/304 ,  H01L21/683 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L24/80 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2223/54426 ,  H01L2224/0217 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80139 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06593

Abstract: A method includes placing a first package component. The first package component includes a first alignment mark and a first dummy alignment mark. A second package component is aligned to the first package component. The second package component includes a second alignment mark and a second dummy alignment mark. The aligning is performed using the first alignment mark for positioning the first package component, and using the second alignment mark for position the second package component. The second package component is bonded to the first package component to form a package, with the first alignment mark being bonded to the second dummy alignment mark.