公开(公告)号：US10854565B2

公开(公告)日：2020-12-01

申请号：US16137774

申请日：2018-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yu Chen ,  Li-Hsien Huang ,  An-Jhih Su ,  Hsien-Wei Chen

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48 ,  H01L21/54

Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.

公开(公告)号：US20200251456A1

公开(公告)日：2020-08-06

申请号：US16857161

申请日：2020-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Po-Hao Tsai ,  Ming-Shih Yeh ,  Ta-Wei Liu

IPC: H01L25/10 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

公开(公告)号：US10290610B2

公开(公告)日：2019-05-14

申请号：US15688893

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  An-Jhih Su ,  Der-Chyang Yeh ,  Hua-Wei Tseng ,  Li-Hui Cheng ,  Po-Hao Tsai ,  Wei-Yu Chen ,  Ming-Shih Yeh

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L21/768 ,  H01L25/00 ,  H01L23/522 ,  H01L23/498

Abstract: A PoP device includes a first package structure, a second package structure and an underfill layer is provided. The first package structure includes a die, a TIV and an encapsulant. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and a portion of sidewalls of the TIV. The second package structure is connected to the first package structure through a connector. The underfill layer is disposed to fill a space between the first package structure and the second package structure. A portion of the underfill layer is disposed between the encapsulant and the TIV to cover a portion of sidewalls of the TIV.

公开(公告)号：US20190131283A1

公开(公告)日：2019-05-02

申请号：US15795280

申请日：2017-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Po-Hao Tsai ,  Ming-Shih Yeh ,  Ta-Wei Liu

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

公开(公告)号：US20190067249A1

公开(公告)日：2019-02-28

申请号：US15688893

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  An-Jhih Su ,  Der-Chyang Yeh ,  Hua-Wei Tseng ,  Li-Hui Cheng ,  Po-Hao Tsai ,  Wei-Yu Chen ,  Ming-Shih Yeh

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L21/768 ,  H01L23/522 ,  H01L25/00

Abstract: A PoP device includes a first package structure, a second package structure and an underfill layer is provided. The first package structure includes a die, a TIV and an encapsulant. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and a portion of sidewalls of the TIV. The second package structure is connected to the first package structure through a connector. The underfill layer is disposed to fill a space between the first package structure and the second package structure. A portion of the underfill layer is disposed between the encapsulant and the TIV to cover a portion of sidewalls of the TIV.

公开(公告)号：US20180366410A1

公开(公告)日：2018-12-20

申请号：US15627449

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  An-Jhih Su ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Ming-Shih Yeh

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first die, at least one through integrated fan-out via and a molding layer. The at least one through integrated fan-out via is aside the first die and includes a seed layer and a metal layer. The molding layer encapsulates the at least one through integrated fan-out via and the first die. Besides, the seed layer surrounds a sidewall of the metal layer and is between the metal layer and the molding layer.

公开(公告)号：US09941248B2

公开(公告)日：2018-04-10

申请号：US15238725

申请日：2016-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Chung Yang ,  An-Jhih Su ,  Hsien-Wei Chen ,  Jo-Mei Wang ,  Wei-Yu Chen

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/03 ,  H01L24/09 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Package structures, PoP devices and methods of forming the same are disclosed. A package structure includes a first chip, a redistribution layer structure, a plurality of UBM pads, a plurality of connectors and a separator. The redistribution layer structure is electrically connected to the first chip. The UBM pads are electrically connected to the redistribution layer structure. The connectors are electrically connected to the UBM pads. The separator is over the redistribution layer structure and surrounds the connectors.

公开(公告)号：US20250087652A1

公开(公告)日：2025-03-13

申请号：US18405844

申请日：2024-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Cheng-Shiuan Wong ,  Chia-Shen Cheng ,  Hsuan-Ting Kuo ,  Hao-Jan Pei ,  Hsiu-Jen Lin ,  Mao-Yen Chang

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

Abstract: A semiconductor package includes an interposer that has a first side and a second side opposing the first side. A semiconductor device that is on the first side of the interposer and an optical device that is on the first side of the interposer and next to the semiconductor device. A first encapsulant layer includes a first portion and a second portion. The first portion of the first encapsulant layer is on the first side of the interposer and along sidewalls of the semiconductor device. A gap is between a first sidewall of the optical device and a second sidewall of the first portion of the first encapsulant layer. A substrate is over the second side of the interposer. The semiconductor device and the optical device are electrically coupled to the substrate through the interposer.

公开(公告)号：US20240234192A1

公开(公告)日：2024-07-11

申请号：US18152340

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Shiuan Wong ,  Chao-Wei Chiu ,  Wei-Yu Chen ,  Chih-Chiang Tsao ,  Hao-Jan Pei ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC: H01L21/683

CPC classification number: H01L21/6836

Abstract: A method includes attaching a carrier to a semiconductor wafer using a release film; removing the carrier from the semiconductor wafer; and performing a treatment process to remove the release film from the semiconductor wafer, the treatment process comprising: flowing an etchant through a diffusion plate within a treatment chamber, the diffusion plate comprising concentric rings separated by dividers, the concentric rings comprising a first concentric ring of holes, a second concentric ring of holes, and a third concentric ring of holes, each of the concentric rings having a different hole density; and performing a cleaning process on the semiconductor wafer.

公开(公告)号：US12020953B2

公开(公告)日：2024-06-25

申请号：US18297897

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Wei-Yu Chen

IPC: H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/495 ,  H01L23/498 ,  H01L25/18 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/49503 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/20 ,  H01L24/28 ,  H01L25/18 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2924/1203 ,  H01L2924/00012

Abstract: A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.