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11.发明授权Semiconductor memory device comprising sense amplifier having P-type sense amplifier and N-type sense amplifiers with different threshold voltages 有权半导体存储器件包括具有P型读出放大器和具有不同阈值电压的N型读出放大器的读出放大器公开(公告)号：US07843751B2
公开(公告)日：2010-11-30
申请号：US12352347
申请日：2009-01-12
IPC分类号： G11C7/02
CPC分类号： G11C11/4091 , G11C7/065 , G11C2207/065 , H01L27/10897
摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.
摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。
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公开(公告)号：US07633833B2
公开(公告)日：2009-12-15
申请号：US12028788
申请日：2008-02-09
IPC分类号： G11C8/00
CPC分类号： G11C7/04 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C2207/2272
摘要： The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.
摘要翻译： 根据本发明的半导体存储器件具有第一延迟电路块，该第一延迟电路块产生在由外部输入指令周期确定的列周期时间内操作的电路块的定时信号，而第二延迟电路阻止其整个延迟 被控制为由外部时钟确定的访问时间与延迟和列周期时间之间的差异。 控制这些延迟电路块，使得每个延迟电路的延迟是根据列等待时间和工作频率的合适值，并且根据工艺中的色散和工作电压以及工作温度的变化控制每个延迟。
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公开(公告)号：US20090086551A1
公开(公告)日：2009-04-02
申请号：US12285204
申请日：2008-09-30
CPC分类号： G11C11/4093 , G06F11/1004 , G11C7/1006 , G11C7/1012 , G11C8/12
摘要： Disclosed is a semiconductor device in which In case a data group output from a first output pin in a first word configuration is output from the first output pin and a second output pin in a second word configuration, and a data group output from a third output pin in a first word configuration is output from the third output pin and a fourth output pin in a second word configuration, the second output pin is arranged adjacent to the first output pin, and the fourth output pin is arranged adjacent to the third output pin.
摘要翻译： 公开了一种半导体器件，其中如果以第一字配置从第一输出引脚输出的数据组以第二字配置从第一输出引脚和第二输出引脚输出，并且从第三输出输出数据组 第一字配置中的引脚以第二字配置从第三输出引脚和第四输出引脚输出，第二输出引脚被布置为与第一输出引脚相邻，并且第四输出引脚被布置为与第三输出引脚 。
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公开(公告)号：US07505299B2
公开(公告)日：2009-03-17
申请号：US11976531
申请日：2007-10-25
CPC分类号： G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10814 , H01L27/10873
摘要： A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.
摘要翻译： 提供了可以实现高速操作或高度集成并同时实现高速操作的半导体存储器件。 晶体管设置在扩散层区域的两侧，用于存储信息的电容器被连接到，并且每个晶体管的其它扩散层区域连接到相同的位线。 当访问存储器单元时，两个晶体管被激活并且读取该信息。 当对存储单元进行写操作时，使用两个晶体管，并将电荷写入电容器。
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公开(公告)号：US20080239865A1
公开(公告)日：2008-10-02
申请号：US12028788
申请日：2008-02-09
IPC分类号： G11C8/00
CPC分类号： G11C7/04 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C2207/2272
摘要： The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.
摘要翻译： 根据本发明的半导体存储器件具有第一延迟电路块，该第一延迟电路块产生在由外部输入指令周期确定的列周期时间内操作的电路块的定时信号，而第二延迟电路阻止其整个延迟 被控制为由外部时钟确定的访问时间与延迟和列周期时间之间的差异。 控制这些延迟电路块，使得每个延迟电路的延迟是根据列等待时间和工作频率的合适值，并且根据工艺中的色散和工作电压以及工作温度的变化控制每个延迟。
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公开(公告)号：US20080175084A1
公开(公告)日：2008-07-24
申请号：US11969223
申请日：2008-01-03
申请人： Satoru AKIYAMA , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
发明人： Satoru AKIYAMA , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , H01L27/10897
摘要： A semiconductor memory device having high integration, low consumption power and high operation speed compatible to each other including a sense amplifier circuit having plural pull-down circuits and a pull-up circuit, in which a transistor constituting one of plural pull-down circuits has a larger constant than that of a transistor constituting other pull-down circuits, for example, a channel length and a channel width, a pull-down circuit having a larger constant of the transistor in the plural pull-down circuits is precedingly activated and then another pull-down circuit and the pull-up circuit are activated to conduct reading and, further, the data line and the precedingly driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.
摘要翻译： 一种具有高集成度，低功耗和高运行速度的半导体存储器件，包括具有多个下拉电路和上拉电路的读出放大器电路，其中构成多个下拉电路中的一个的晶体管具有 比构成其他下拉电路的晶体管（例如沟道长度和沟道宽度）的常数大的常数，在多个下拉电路中具有较大的晶体管常数的下拉电路先前被激活，然后 另一个下拉电路和上拉电路被激活以进行读取，此外，数据线和先前驱动的下拉电路通过NMOS晶体管连接，并且NMOS晶体管被激活或失活以控制激活或 下拉电路失活。
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公开(公告)号：US20080017904A1
公开(公告)日：2008-01-24
申请号：US11773990
申请日：2007-07-06
申请人： Satoru AKIYAMA , Ryuta Tsuchiya , Tomonori Sekiguchi , Riichiro Takemura , Masayuki Nakamura , Yasushi Yamazaki , Shigeru Shiratake
发明人： Satoru AKIYAMA , Ryuta Tsuchiya , Tomonori Sekiguchi , Riichiro Takemura , Masayuki Nakamura , Yasushi Yamazaki , Shigeru Shiratake
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10894 , G11C7/18 , G11C11/404 , G11C11/4097 , H01L27/10876 , H01L27/10891 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： A DRAM capable of realizing reduced power consumption, high-speed operation, and high reliability is provided. A gate electrode configuring a memory cell transistor of the DRAM is composed of an n-type polysilicon film and a W (tungsten) film stacked thereon. A part of the polysilicon film is embedded in a trench formed in a silicon substrate in order to elongate the effective channel length of the memory cell transistor. The other part of the polysilicon film is located above the trench, and an upper surface thereof is located above a surface of the silicon substrate (p-type well). Therefore, distances between the W film and a source and drain (n-type semiconductor regions) are ensured.
摘要翻译： 提供了能够实现降低功耗，高速运行和高可靠性的DRAM。 构成DRAM的存储单元晶体管的栅电极由n型多晶硅膜和堆叠在其上的W（钨）膜构成。 为了延长存储单元晶体管的有效沟道长度，多晶硅膜的一部分嵌入在硅衬底中形成的沟槽中。 多晶硅膜的另一部分位于沟槽上方，其上表面位于硅衬底的表面上方（p型阱）。 因此，确保W膜与源极和漏极（n型半导体区域）之间的距离。
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公开(公告)号：US20070153617A1
公开(公告)日：2007-07-05
申请号：US11652012
申请日：2007-01-11
申请人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
发明人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
IPC分类号： G11C7/02
CPC分类号： G11C7/1051 , G11C5/025 , G11C7/02 , G11C7/1006 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C11/405 , G11C11/4096 , G11C2207/107
摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.
摘要翻译： 采用具有随机访问的数据寄存器的单交叉存储单元阵列的DRAM，只要芯片被外部访问即可。 当记录在数据寄存器中的数据项被同时写入存储单元阵列时，对数据项进行编码。 当将数据项从存储单元阵列读入数据寄存器时，数据项被解码。 由于从读数导出的阵列噪声减小，因此边缘被增强。 另外，DRAM的存取时间也减少了。
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公开(公告)号：US20060158924A1
公开(公告)日：2006-07-20
申请号：US11280170
申请日：2005-11-17
IPC分类号： G11C11/24
CPC分类号： G11C11/4094 , G11C7/12 , G11C7/18 , G11C11/4074 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10882
摘要： A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold voltage, MVT: mid threshold voltage, HVT: high threshold voltage) of a memory cell transistor is written into a storage node of a capacitor via the memory cell transistor. Thereafter, when a plate line connected to a plate side of the capacitor is driven from voltage VPL to voltage VPH and the voltage of the storage node is increased due to coupling, the voltage VDL of the bit line is reduced to the voltage VDP, and the voltage excessively written into the storage node is reduced in accordance with a level of a threshold voltage of the memory cell transistor, thereby reducing a variation in the voltage of the storage node due to a variation in the threshold voltage.
摘要翻译： 从外部输入写命令，位线的电压变为VDL和VSS，以及根据存储单元的阈值电压（LVT：低阈值电压，MVT：中间阈值电压，HVT：高阈值电压）的电压 晶体管经由存储单元晶体管写入电容器的存储节点。 此后，当连接到电容器的板侧的板线从电压VPL驱动到电压VPH并且存储节点的电压由于耦合而增加时，位线的电压VDL被降低到电压VDP，并且 根据存储单元晶体管的阈值电压的电平降低过度写入存储节点的电压，从而减小由于阈值电压的变化引起的存储节点的电压的变化。
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公开(公告)号：US06917552B2
公开(公告)日：2005-07-12
申请号：US10671464
申请日：2003-09-29
IPC分类号： G11C7/00 , G11C7/06 , G11C11/4091 , G11C11/4097
CPC分类号： G11C7/062 , G11C7/065 , G11C11/4091 , G11C11/4097
摘要： Disclosed is a sense amplifier arrangement that achieves high-speed access and shorter cycle time when array voltage is lowered in a DRAM. In a TG clocking sense system to separate data lines between the array side and the sense amplifier side in an early stage of a sensing period, a restore amplifier RAP is added, which amplifies data lines on the array side by referring to the data in the sense amplifier, and the restore amplifier is driven by a voltage VDH higher than the array voltage VDL. As a result, high-speed sense operation of the TG clocking system is made compatible with high-speed restore operation of overdrive system, and it is possible to achieve high-speed access operation and shorter cycle time.
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