公开(公告)号：US20130316507A1

公开(公告)日：2013-11-28

申请号：US13981856

申请日：2011-08-24

申请人： Yu Saitoh ,  Masaya Okada ,  Masaki Ueno ,  Makoto Kiyama

发明人： Yu Saitoh ,  Masaya Okada ,  Masaki Ueno ,  Makoto Kiyama

IPC分类号： H01L29/20

CPC分类号： H01L29/2003 ,  H01L29/66462 ,  H01L29/7371 ,  H01L29/7788 ,  H01L29/7789

摘要： A method for manufacturing a heterojunction field effect transistor 1 comprises the steps of: epitaxially growing a drift layer 20a on a support substrate 10; epitaxially growing a current blocking layer 20b which is a p-type semiconductor layer on the drift layer 20a at a temperature equal to or higher than 1000° C. by using hydrogen gas as a carrier gas; and epitaxially growing a contact layer 20c on the current blocking layer 20b by using at least one gas selected from the group consisting of nitrogen gas, argon gas, helium gas, and neon gas as a carrier gas.

摘要翻译： 异质结场效应晶体管1的制造方法包括以下步骤：在支撑基板10上外延生长漂移层20a; 通过使用氢气作为载气，在等于或高于1000℃的温度下外延生长漂移层20a上的p型半导体层的电流阻挡层20b; 并且使用从由氮气，氩气，氦气和氖气组成的组中选择的至少一种气体作为载气，在电流阻挡层20b上外延生长接触层20c。

公开(公告)号：US08890239B2

公开(公告)日：2014-11-18

申请号：US13884221

申请日：2011-07-26

申请人： Seiji Yaegashi ,  Makoto Kiyama ,  Mitsunori Yokoyama ,  Kazutaka Inoue ,  Masaya Okada ,  Yu Saitoh

发明人： Seiji Yaegashi ,  Makoto Kiyama ,  Mitsunori Yokoyama ,  Kazutaka Inoue ,  Masaya Okada ,  Yu Saitoh

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/20

CPC分类号： H01L29/7802 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/66712 ,  H01L29/7788 ,  H01L29/7789

摘要： In a vertical semiconductor device including a channel in an opening, a semiconductor device whose high-frequency characteristics can be improved and a method for producing the semiconductor device are provided. The semiconductor device includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. An opening 28 extends from a top layer and reaches the n-type GaN-based drift layer. The semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, a drain electrode D, and a gate electrode G located on the regrown layer. Assuming that the source electrode serving as one electrode and the drain electrode serving as the other electrode constitute a capacitor, the semiconductor device includes a capacitance-decreasing structure that decreases the capacitance of the capacitor.

摘要翻译： 在包括开口中的沟道的垂直半导体器件中，提供了可以提高其高频特性的半导体器件和制造半导体器件的方法。 半导体器件包括n型GaN基漂移层4 / p型GaN基阻挡层6 / n型GaN基接触层7.开口28从顶层延伸并到达n型GaN- 基漂移层。 半导体器件包括以覆盖开口的方式定位的再生长层27，包括电子漂移层22和电子供给层26的再生长层27，源电极S，漏电极D和位于 再生长层。 假设用作一个电极的源极和用作另一个电极的漏电极构成电容器，则半导体器件包括降低电容器的电容的电容减小结构。

公开(公告)号：US08729562B2

公开(公告)日：2014-05-20

申请号：US13498767

申请日：2010-06-24

申请人： Masaya Okada ,  Makoto Kiyama

发明人： Masaya Okada ,  Makoto Kiyama

IPC分类号： H01L29/15

CPC分类号： H01L29/7786 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/7789

摘要： There are provided a high current semiconductor device that has low on-resistance, high mobility, and good pinch-off characteristics and in which a kink phenomenon is not easily caused even if a drain voltage is increased, and a method for producing the semiconductor device. The semiconductor device of the present invention includes a GaN-based layered body 15 having an opening 28, a regrown layer 27 including a channel, a gate electrode G, a source electrode S, and a drain electrode D. The regrown layer 27 includes an electron transit layer 22 and an electron supply layer 26. The GaN-based layered body includes a p-type GaN layer 6 whose end surface is covered by the regrown layer in the opening, and a p-side electrode 11 that is in ohmic contact with the p-type GaN layer is disposed.

摘要翻译： 提供了具有低导通电阻，高迁移率和良好的夹断特性的高电流半导体器件，并且即使漏极电压增加也不容易引起扭结现象，并且制造半导体器件的方法 。 本发明的半导体器件包括具有开口28的GaN基层叠体15，包括沟道的再生长层27，栅电极G，源电极S和漏电极D.再生层27包括： 电子转移层22和电子供给层26.该GaN基层叠体包括端面被开口部中的再生长层覆盖的p型GaN层6和与欧姆接触的p侧电极11 配置p型GaN层。

公开(公告)号：US08476086B2

公开(公告)日：2013-07-02

申请号：US11947752

申请日：2007-11-29

申请人： Shinsuke Fujiwara ,  Takashi Sakurada ,  Makoto Kiyama ,  Yusuke Yoshizumi

发明人： Shinsuke Fujiwara ,  Takashi Sakurada ,  Makoto Kiyama ,  Yusuke Yoshizumi

IPC分类号： H01L33/00

CPC分类号： H01L29/2003 ,  C30B25/02 ,  C30B29/406 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02658

摘要： Method of high-yield manufacturing superior semiconductor devices includes: a step of preparing a GaN substrate having a ratio St/S—of collective area (St cm2) of inversion domains in, to total area (S cm2) of the principal face of, the GaN substrate—of no more than 0.5, with the density along the (0001) Ga face, being the substrate principal face, of inversion domains whose surface area where the polarity in the [0001] direction is inverted with respect to the principal domain (matrix) is 1 μm2 or more being D cm−2; and a step of growing on the GaN substrate principal face an at least single-lamina semiconductor layer to form semiconductor devices in which the product Sc×D of the area Sc of the device principal faces, and the density D of the inversion domains is made less than 2.3.

摘要翻译： 高产率制造方法优异的半导体器件包括：制备具有反向畴的总面积（St cm2）的St / S-与主面的总面积（S cm2）的GaN衬底的步骤， 所述GaN衬底的不大于0.5，其中沿[0001]方向的极性的表面积相对于所述主结构域反转的反转畴的（0001）Ga面的密度（作为衬底主面） （矩阵）为1mum2以上为Dcm-2; 并且在GaN衬底主体上生长至少单层半导体层以形成半导体器件的步骤，其中器件主要面积Sc的乘积Sc×D面向反射区域的密度D 小于2.3。

公开(公告)号：US20100207138A1

公开(公告)日：2010-08-19

申请号：US12767783

申请日：2010-04-26

申请人： Seiji Nakahata ,  Hideaki Nakahata ,  Koji Uematsu ,  Makoto Kiyama ,  Youichi Nagai ,  Takao Nakamura

发明人： Seiji Nakahata ,  Hideaki Nakahata ,  Koji Uematsu ,  Makoto Kiyama ,  Youichi Nagai ,  Takao Nakamura

IPC分类号： H01L33/30 ,  H01L29/20

CPC分类号： H01L33/007 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02645 ,  H01L33/0075 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

摘要： Group III nitride semiconductor crystals of a size appropriate for semiconductor devices and methods for manufacturing the same, Group III nitride semiconductor devices and methods for manufacturing the same, and light-emitting appliances. A method of manufacturing a Group III nitride semiconductor crystal includes a process of growing at least one Group III nitride semiconductor crystal substrate on a starting substrate, a process of growing at least one Group III nitride semiconductor crystal layer on the Group III nitride semiconductor crystal substrate, and a process of separating a Group III nitride semiconductor crystal, constituted by the Group III nitride semiconductor crystal substrate and the Group III nitride semiconductor crystal layer, from the starting substrate, and is characterized in that the Group III nitride semiconductor crystal is 10 μm or more but 600 μm or less in thickness, and is 0.2 mm or more but 50 mm or less in width.

摘要翻译： 尺寸适合于半导体器件的III族氮化物半导体晶体及其制造方法，III族氮化物半导体器件及其制造方法以及发光器具。 制造III族氮化物半导体晶体的方法包括在起始衬底上生长至少一种III族氮化物半导体晶体衬底的工艺，在III族氮化物半导体晶体衬底上生长至少一种III族氮化物半导体晶体层的工艺 以及从起始基板分离由III族氮化物半导体晶体基板和III族氮化物半导体晶体层构成的III族氮化物半导体晶体的工序，其特征在于，所述III族氮化物半导体晶体为10μm 以上且600μm以下，宽度为0.2mm以上且50mm以下。

公开(公告)号：US07687822B2

公开(公告)日：2010-03-30

申请号：US11727425

申请日：2007-03-27

申请人： Youichi Nagai ,  Makoto Kiyama ,  Takao Nakamura ,  Takashi Sakurada ,  Katsushi Akita ,  Koji Uematsu ,  Ayako Ikeda ,  Koji Katayama ,  Susumu Yoshimoto

发明人： Youichi Nagai ,  Makoto Kiyama ,  Takao Nakamura ,  Takashi Sakurada ,  Katsushi Akita ,  Koji Uematsu ,  Ayako Ikeda ,  Koji Katayama ,  Susumu Yoshimoto

IPC分类号： H01L33/00

CPC分类号： H01L33/32 ,  H01L33/20 ,  H01L33/382 ,  H01L33/505 ,  H01L33/507 ,  H01L33/58 ,  H01L2224/05573 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/2076 ,  H01L2224/05599 ,  H01L2924/00011 ,  H01L2224/45099

摘要： In order to provide light emitting devices which have simple constructions and thus can be fabricated easily, and can stably provide high light emission efficiencies for a long time period, a light emitting device includes an n-type nitride semiconductor layer at a first main surface side of a nitride semiconductor substrate, a p-type nitride semiconductor layer placed more distantly from the nitride semiconductor substrate than the n-type nitride semiconductor layer at the first main surface side and a light emitting layer placed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer at the first main surface side. The nitride semiconductor substrate has a resistivity of 0.5 Ω·cm or less and the p-type nitride semiconductor layer side is down-mounted so that light is emitted from the second main surface of the nitride semiconductor substrate at the opposite side from the first main surface.

摘要翻译： 为了提供具有简单结构并因此可以容易地制造并且可以长期稳定地提供高发光效率的发光器件，发光器件在第一主表面侧包括n型氮化物半导体层 的氮化物半导体衬底，比在第一主表面侧的n型氮化物半导体层更远离氮化物半导体衬底设置的p型氮化物半导体层，以及放置在n型氮化物半导体层和 在第一主表面侧的p型氮化物半导体层。 氮化物半导体衬底的电阻率为0.5Ω·cm·cm·cm以下，p型氮化物半导体层一侧被下降，使得从氮化物半导体衬底的第二主表面与第一 主表面。

公开(公告)号：US20080265258A1

公开(公告)日：2008-10-30

申请号：US11569066

申请日：2006-03-03

申请人： Tatsuya Tanabe ,  Makoto Kiyama ,  Kouhei Miura ,  Takashi Sakurada

发明人： Tatsuya Tanabe ,  Makoto Kiyama ,  Kouhei Miura ,  Takashi Sakurada

IPC分类号： H01L29/205 ,  H01L29/778

CPC分类号： H01L29/66462 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02587 ,  H01L29/7787

摘要： Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be decreased. In a high electron mobility transistor 1, a supporting substrate 3 is composed of AlN, AlGaN, or GaN. An AlyGa1-yN epitaxial layer 5 has a surface roughness (RMS) of 0.25 mm or less, wherein the surface roughness is defined by a square area measuring 1 μm per side. A GaN epitaxial layer 7 is provided between the AlyGa1-yN supporting substrate 3 and the AlyGa1-yN epitaxial layer 5. A Schottky electrode 9 is provided on the AlyGa1-yN epitaxial layer 5. A first ohmic electrode 11 is provided on the AlyGa1-yN epitaxial layer 5. A second ohmic electrode 13 is provided on the AlyGa1-yN epitaxial layer 5. One of the first and second ohmic electrodes 11 and 13 constitutes a source electrode, and the other constitutes a drain electrode. The Schottky electrode 9 constitutes a gate electrode of the high electron mobility transistor 1.

摘要翻译： 提供可以减少来自肖特基电极的漏电流的III族氮化物半导体器件。 在高电子迁移率晶体管1中，支撑基板3由AlN，AlGaN或GaN构成。 Al钇1-y N外延层5具有0.25mm或更小的表面粗糙度（RMS），其中表面粗糙度由测量1的正方形面积 妈妈每边。 在AlGaN外延层7之间设置有支撑衬底3的Al 1 Y y-N支撑衬底和Al 1 Al- 在N外延层5上设置肖特基电极9.设置第一欧姆电极11和第一欧姆电极11。 在Al钇1-y N外延层5上。第二欧姆电极13设置在Al钇1 Ga -Y / N外延层5.第一和第二欧姆电极11和13中的一个构成源电极，另一个构成漏电极。 肖特基电极9构成高电子迁移率晶体管1的栅电极。

公开(公告)号：US20070164306A1

公开(公告)日：2007-07-19

申请号：US10598934

申请日：2005-05-13

申请人： Seiji Nakahata ,  Hideaki Nakahata ,  Koji Uematsu ,  Makoto Kiyama ,  Youichi Nagai ,  Takao Nakamura

发明人： Seiji Nakahata ,  Hideaki Nakahata ,  Koji Uematsu ,  Makoto Kiyama ,  Youichi Nagai ,  Takao Nakamura

IPC分类号： H01L33/00 ,  H01L21/00

CPC分类号： H01L33/007 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02645 ,  H01L33/0075 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

摘要： The invention provides Group III nitride semiconductor crystals of a size appropriate for semiconductor devices and methods for manufacturing the same, Group III nitride semiconductor devices and methods for manufacturing the same, and light-emitting appliances. A method of manufacturing a Group III nitride semiconductor crystal includes a process of growing at least one Group III nitride semiconductor crystal substrate on a starting substrate, a process of growing at least one Group III nitride semiconductor crystal layer on the Group III nitride semiconductor crystal substrate, and a process of separating a Group III nitride semiconductor crystal, constituted by the Group III nitride semiconductor crystal substrate and the Group III nitride semiconductor crystal layer, from the starting substrate, and is characterized in that the Group III nitride semiconductor crystal is 10 μm or more but 600 μm or less in thickness, and is 0.2 mm or more but 50 mm or less in width.

摘要翻译： 本发明提供适合于半导体器件的尺寸的III族氮化物半导体晶体及其制造方法，III族氮化物半导体器件及其制造方法以及发光器具。 制造III族氮化物半导体晶体的方法包括在起始衬底上生长至少一种III族氮化物半导体晶体衬底的工艺，在III族氮化物半导体晶体衬底上生长至少一种III族氮化物半导体晶体层的工艺 以及从起始衬底分离由III族氮化物半导体晶体衬底和III族氮化物半导体晶体层构成的III族氮化物半导体晶体的工序，其特征在于，所述III族氮化物半导体晶体为10μm 以上且600μm以下，宽度为0.2mm以上且50mm以下。

公开(公告)号：US06756607B2

公开(公告)日：2004-06-29

申请号：US10249710

申请日：2003-05-01

申请人： Masashi Yamashita ,  Mitsutaka Tsubokura ,  Makoto Kiyama

发明人： Masashi Yamashita ,  Mitsutaka Tsubokura ,  Makoto Kiyama

IPC分类号： H01L2358

CPC分类号： H01L22/14

摘要： Backgate-characteristics determination method and device that make for curtailing the fabrication of semiconductor circuit elements having defective backgate-characteristics. Initially a first C-V curve 30 representing the relation between a voltage applied to the obverse face of a wafer 20 serving as a substrate for semiconductor circuit elements, and its capacitance, is found. Next, a second C-V curve 32 is found through applying a voltage to the reverse face of the wafer 20. The backgate characteristics for the semiconductor circuit elements are determined based on a voltage-shift amount 34 for the wafer 20, found from the first C-V curve 30 and the second C-V curve 32.

摘要翻译： 背栅特性确定方法和装置，其用于抑制具有缺陷背栅特性的半导体电路元件的制造。 首先，找到表示施加到用作半导体电路元件的基板的晶片20的正面的电压与其电容之间的关系的第一C-V曲线30。 接下来，通过向晶片20的反面施加电压来发现第二CV曲线32.半导体电路元件的背栅特性基于从第一CV找到的晶片20的电压移位量34来确定 曲线30和第二CV曲线32。

公开(公告)号：US06184498B2

公开(公告)日：2001-02-06

申请号：US09397382

申请日：1999-09-16

申请人： Makoto Kiyama

发明人： Makoto Kiyama

IPC分类号： F27B514

CPC分类号： H01L22/20 ,  H01L21/324 ,  H01L22/12

摘要： An apparatus for thermally processing a semiconductor wafer includes a susceptor to support the wafer, a heater arrangement to differentially heat the wafer and provide a temperature distribution on said wafer, a radiation thermometer for measuring the temperature distribution, and means for controlling and varying the temperature distribution. The heater arrangement particularly includes a first heater to heat an edge of the wafer, around a second heater to heat a center area of the wafer. With this apparatus, the rate of change of the temperature and the temperature distribution of the wafer can be controlled within tolerable limits to avoid slip line generation. Also, the relative stress state of the wafer edge and the wafer center can be influenced by differential heating of the edge and the center.

摘要翻译： 一种用于热处理半导体晶片的装置包括：用于支撑晶片的基座，用于差分加热晶片并在所述晶片上提供温度分布的加热器装置，用于测量温度分布的辐射温度计，以及用于控制和改变温度的装置 分配。 加热器装置特别地包括加热晶片的边缘的第一加热器，围绕第二加热器加热晶片的中心区域。 利用该装置，可以将晶片的温度和温度分布的变化率控制在可容忍的极限内，以避免产生滑移线。 此外，晶片边缘和晶片中心的相对应力状态可能受到边缘和中心的差分加热的影响。