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公开(公告)号：US08476086B2
公开(公告)日：2013-07-02
申请号：US11947752
申请日：2007-11-29
IPC分类号： H01L33/00
CPC分类号： H01L29/2003 , C30B25/02 , C30B29/406 , H01L21/02389 , H01L21/02433 , H01L21/02458 , H01L21/02516 , H01L21/0254 , H01L21/0262 , H01L21/02658
摘要： Method of high-yield manufacturing superior semiconductor devices includes: a step of preparing a GaN substrate having a ratio St/S—of collective area (St cm2) of inversion domains in, to total area (S cm2) of the principal face of, the GaN substrate—of no more than 0.5, with the density along the (0001) Ga face, being the substrate principal face, of inversion domains whose surface area where the polarity in the [0001] direction is inverted with respect to the principal domain (matrix) is 1 μm2 or more being D cm−2; and a step of growing on the GaN substrate principal face an at least single-lamina semiconductor layer to form semiconductor devices in which the product Sc×D of the area Sc of the device principal faces, and the density D of the inversion domains is made less than 2.3.
摘要翻译： 高产率制造方法优异的半导体器件包括：制备具有反向畴的总面积（St cm2）的St / S-与主面的总面积（S cm2）的GaN衬底的步骤， 所述GaN衬底的不大于0.5，其中沿[0001]方向的极性的表面积相对于所述主结构域反转的反转畴的（0001）Ga面的密度（作为衬底主面） （矩阵）为1mum2以上为Dcm-2; 并且在GaN衬底主体上生长至少单层半导体层以形成半导体器件的步骤，其中器件主要面积Sc的乘积Sc×D面向反射区域的密度D 小于2.3。
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公开(公告)号：US20080128706A1
公开(公告)日：2008-06-05
申请号：US11947752
申请日：2007-11-29
IPC分类号： H01L29/20 , H01L21/205
CPC分类号： H01L29/2003 , C30B25/02 , C30B29/406 , H01L21/02389 , H01L21/02433 , H01L21/02458 , H01L21/02516 , H01L21/0254 , H01L21/0262 , H01L21/02658
摘要： Method of high-yield manufacturing superior semiconductor devices includes: a step of preparing a GaN substrate having a ratio St/S—of collective area (St cm2) of inversion domains in, to total area (S cm2) of the principal face of, the GaN substrate—of no more than 0.5, with the density along the (0001) Ga face, being the substrate principal face, of inversion domains whose surface area where the polarity in the [0001] direction is inverted with respect to the principal domain (matrix) is 1 μm2 or more being D cm−2; and a step of growing on the GaN substrate principal face an at least single-lamina semiconductor layer to form semiconductor devices in which the product Sc×D of the area Sc of the device principal faces, and the density D of the inversion domains is made less than 2.3.
摘要翻译： 高产量制造方法优异的半导体器件包括：制备具有集体面积的比率S / T / S的GaN衬底的步骤， （0001）的浓度，在GaN基板的主面的总面积（S cm 2以上）不大于0.5的情况下， 在[0001]方向上的极性相对于主域（矩阵）反转的表面积为反向畴的Ga面作为衬底主面为1μm以上为D cm 2; 并且在GaN衬底主体上生长至少单层半导体层以形成半导体器件的步骤，其中产品S区域S D的区域S < 器件主面，反型域的密度D小于2.3。
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3.发明授权公开(公告)号：US07998836B1
公开(公告)日：2011-08-16
申请号：US12912932
申请日：2010-10-27
申请人： Hiromu Shiomi , Shinsuke Fujiwara , Yu Saitoh , Makoto Kiyama
发明人： Hiromu Shiomi , Shinsuke Fujiwara , Yu Saitoh , Makoto Kiyama
IPC分类号： H01L21/30
CPC分类号： H01L29/66219 , H01L29/2003 , H01L29/66204 , H01L29/861 , H01L29/872
摘要： A method of fabricating a gallium nitride-based semiconductor electronic device is provided, the method preventing a reduction in adhesiveness between a gallium nitride-based semiconductor layer and a conductive substrate. A substrate 11 is prepared. The substrate 11 has a first surface 11a and a second surface 11b, the first surface 11a allowing a gallium nitride-based semiconductor to be deposited thereon. The substrate 11 includes a support 13 of a material different from the gallium nitride-based semiconductor. The support is exposed on the second surface 11b of the substrate 11. An array of grooves 15 is provided in the second surface 11b. A semiconductor region including at least one gallium nitride-based semiconductor layer is deposited on the first surface 11a of the substrate 11, and thereby an epitaxial substrate E is fabricated. A conductive substrate 33 is bonded to the epitaxial substrate E such that the semiconductor region 17 is provided between the first surface 11a of the substrate 11 and the conductive substrate E. Subsequently, the second surface 11b is irradiated with laser light for laser lift-off.
摘要翻译： 提供了一种制造氮化镓基半导体电子器件的方法，该方法防止了氮化镓基半导体层与导电基片之间的粘附性的降低。 制备基板11。 基板11具有第一表面11a和第二表面11b，第一表面11a允许沉积氮化镓基半导体。 基板11包括与氮化镓基半导体不同的材料的支撑体13。 支撑体暴露在基板11的第二表面11b上。在第二表面11b中设置有一组槽15。 包括至少一个氮化镓基半导体层的半导体区域沉积在衬底11的第一表面11a上，由此制造外延衬底E。 将导电基板33接合到外延基板E，使得半导体区域17设置在基板11的第一表面11a和导电基板E之间。接着，用激光照射激光剥离第二表面11b 。
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4.发明授权GaN single-crystal mass and method of its manufacture, and semiconductor device and method of its manufacture 有权GaN单晶质量及其制造方法，半导体器件及其制造方法公开(公告)号：US08294245B2
公开(公告)日：2012-10-23
申请号：US12797617
申请日：2010-06-10
申请人： Hideaki Nakahata , Shinsuke Fujiwara , Takashi Sakurada , Yoshiyuki Yamamoto , Seiji Nakahata , Tomoki Uemura
发明人： Hideaki Nakahata , Shinsuke Fujiwara , Takashi Sakurada , Yoshiyuki Yamamoto , Seiji Nakahata , Tomoki Uemura
IPC分类号： H01L29/20
CPC分类号： H01L29/872 , C30B25/00 , C30B29/406 , H01L21/02008 , H01L21/0237 , H01L21/0254 , H01L21/0262 , H01L29/2003 , H01L29/205
摘要： Affords a GaN single-crystal mass, a method of its manufacture, and a semiconductor device and method of its manufacture, whereby when the GaN single-crystal mass is being grown, and when the grown GaN single-crystal mass is being processed into a substrate or like form, as well as when an at least single-lamina semiconductor layer is being formed onto a single-crystal GaN mass in substrate form to manufacture semiconductor devices, cracking is controlled to a minimum. The GaN single-crystal mass 10 has a wurtzitic crystalline structure and, at 30° C., its elastic constant C11 is from 348 GPa to 365 GPa and its elastic constant C13 is from 90 GPa to 98 GPa; alternatively its elastic constant C11 is from 352 GPa to 362 GPa.
摘要翻译： 提供GaN单晶体，其制造方法以及其制造的半导体器件及其制造方法，由此当生长GaN单晶质量时，并且当将生长的GaN单晶体块加工成 衬底或类似形式，以及当至少单层GaN半导体层以衬底形式形成在单晶GaN块上以制造半导体器件时，将裂纹控制到最小。 GaN单晶块10具有纤锌矿结晶结构，在30℃下，其弹性常数C11为348GPa至365GPa，其弹性常数C13为90GPa至98GPa; 或者其弹性常数C11为352GPa至362GPa。
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5.发明授权公开(公告)号：US08147612B2
公开(公告)日：2012-04-03
申请号：US12298332
申请日：2007-04-24
申请人： Tomoki Uemura , Takashi Sakurada , Shinsuke Fujiwara , Takuji Okahisa , Koji Uematsu , Hideaki Nakahata
发明人： Tomoki Uemura , Takashi Sakurada , Shinsuke Fujiwara , Takuji Okahisa , Koji Uematsu , Hideaki Nakahata
IPC分类号： C30B21/02
CPC分类号： H01L21/02623 , C30B25/186 , C30B25/20 , C30B29/406 , H01L21/02389 , H01L21/0254 , H01L21/0262 , H01L21/02658
摘要： There is provided a method for fabricating a gallium nitride crystal with low dislocation density, high crystallinity, and resistance to cracking during polishing of sliced pieces by growing the gallium nitride crystal using a gallium nitride substrate including dislocation-concentrated regions or inverted-polarity regions as a seed crystal substrate. Growing a gallium nitride crystal 79 at a growth temperature higher than 1,100° C. and equal to or lower than 1,300° C. so as to bury dislocation-concentrated regions or inverted-polarity regions 17a reduces dislocations inherited from the dislocation-concentrated regions or inverted regions 17a, thus preventing new dislocations from occurring over the dislocation-concentrated regions or inverted-polarity regions 17a. This also increases the crystallinity of the gallium nitride crystal 79 and its resistance to cracking during the polishing.
摘要翻译： 提供了通过使用包括位错集中区域或反极性区域的氮化镓衬底生长氮化镓晶体来制造在切片的研磨期间具有低位错密度，高结晶度和耐龟裂性的氮化镓晶体的方法， 晶种基片。 在高于1100℃并且等于或低于1300℃的生长温度下生长氮化镓晶体79，以便掩埋位错集中区域或反极性区域17a减少从位错集中区域遗留的位错或 反转区域17a，从而防止在位错集中区域或反极性区域17a上发生新的位错。 这也增加了氮化镓晶体79的结晶度及其在抛光过程中的抗开裂性。
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公开(公告)号：US09005362B2
公开(公告)日：2015-04-14
申请号：US13115560
申请日：2011-05-25
CPC分类号： H01L21/02389 , C30B25/18 , C30B29/403 , H01L21/0243 , H01L21/02433 , H01L21/0254 , H01L21/0262 , H01L21/02658
摘要： The present invention is to provide a method for growing a group III nitride crystal that has a large size and has a small number of pits formed in the main surface of the crystal by using a plurality of tile substrates. A method for growing a group III nitride crystal includes a step of preparing a plurality of tile substrates 10 including main surfaces 10m having a shape of a triangle or a convex quadrangle that allows two-dimensional close packing of the plurality of tile substrates; a step of arranging the plurality of tile substrates 10 so as to be two-dimensionally closely packed such that, at any point across which vertexes of the plurality of tile substrates 10 oppose one another, 3 or less of the vertexes oppose one another; and a step of growing a group III nitride crystal 20 on the main surfaces 10m of the plurality of tile substrates arranged.
摘要翻译： 本发明提供一种通过使用多个瓦片基板来生长具有大尺寸并且具有少量形成在晶体的主表面中的凹坑的III族氮化物晶体的方法。 用于生长III族氮化物晶体的方法包括制备多个瓦片基板10的步骤，该瓦片基板10包括允许多个瓦片基板的二维密封的具有三角形形状的主表面10m或凸形四边形; 将多个瓦片基板10布置成二维紧密堆叠的步骤，使得在多个瓦片基板10的顶点彼此相对的任何点处，3个或更少的顶点彼此相对; 以及在布置的多个瓦片基板的主表面10m上生长III族氮化物晶体20的步骤。
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7.发明授权Process for producing Si(1-v-w-x)CwAlxNv base material, process for producing epitaxial wafer, Si(1-v-w-x)CwAlxNv base material, and epitaxial wafer 有权Si（1-v-w-x）CwAlxNv基材的制造方法，外延晶片的制造方法，Si（1-v-w-x）CwAlxNv母材，外延片公开(公告)号：US08715414B2
公开(公告)日：2014-05-06
申请号：US12989036
申请日：2009-04-17
IPC分类号： C30B29/38
CPC分类号： C30B29/36 , C23C4/185 , C23C16/34 , C30B23/02 , C30B25/02 , C30B29/403 , H01L21/0237 , H01L21/02378 , H01L21/02381 , H01L21/02389 , H01L21/0242 , H01L21/02529 , H01L21/0254 , H01L21/0262 , H01L21/02631
摘要： There are provided a Si(1-v-w-x)CwAlxNv substrate that achieves high crystallinity and low costs, an epitaxial wafer, and manufacturing methods thereof.A method for manufacturing a Si(1-v-w-x)CwAlxNv substrate according to the present invention includes the steps of preparing a different type of substrate 11 and growing a Si(1-v-w-x)CwAlxNv layer having a main surface on the different type of substrate 11. The component ratio x+v at the main surface of the Si(1-v-w-x)CwAlxNv layer is 0
摘要翻译： 提供了实现高结晶度和低成本的Si（1-v-w-x）C w Al x N v衬底，外延晶片及其制造方法。 根据本发明的用于制造Si（1-vwx）CwAlxNv衬底的方法包括以下步骤：制备不同类型的衬底11并在不同类型的衬底上生长具有主表面的Si（1-vwx）C w Al x N v层 Si（1-vwx）CwAlxNv层的主表面的分量比x + v为0
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公开(公告)号：US08658517B2
公开(公告)日：2014-02-25
申请号：US13643206
申请日：2011-11-10
申请人： Issei Satoh , Yuki Seki , Koji Uematsu , Yoshiyuki Yamamoto , Hideki Matsubara , Shinsuke Fujiwara , Masashi Yoshimura
发明人： Issei Satoh , Yuki Seki , Koji Uematsu , Yoshiyuki Yamamoto , Hideki Matsubara , Shinsuke Fujiwara , Masashi Yoshimura
IPC分类号： H01L21/20
摘要： The present method of manufacturing a GaN-based film includes the steps of preparing a composite substrate, the composite substrate including a support substrate in which a coefficient of thermal expansion in a main surface is more than 0.8 time and less than 1.2 times as high as a coefficient of thermal expansion of GaN crystal in a direction of a axis and a single crystal film arranged on a side of the main surface of the support substrate, the single crystal film having threefold symmetry with respect to an axis perpendicular to a main surface of the single crystal film, and forming a GaN-based film on the main surface of the single crystal film in the composite substrate. Thus, a method of manufacturing a GaN-based film capable of manufacturing a GaN-based film having a large main surface area and less warpage is provided.
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9.发明授权Epitaxial wafer, method for manufacturing gallium nitride semiconductor device, gallium nitride semiconductor device and gallium oxide wafer 失效外延晶片，氮化镓半导体器件的制造方法，氮化镓半导体器件和氧化镓晶片公开(公告)号：US08592289B2
公开(公告)日：2013-11-26
申请号：US13148543
申请日：2010-02-04
CPC分类号： H01L21/0242 , C30B25/18 , C30B29/16 , C30B29/403 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L29/045 , H01L29/2003 , H01L29/66462 , H01L29/7787 , H01L33/007 , H01L33/16
摘要： A gallium nitride based semiconductor device is provided which includes a gallium nitride based semiconductor film with a flat c-plane surface provided on a gallium oxide wafer. A light emitting diode LED includes a gallium oxide support base 32 having a primary surface 32a of monoclinic gallium oxide, and a laminate structure 33 of Group III nitride. A semiconductor mesa of the laminate structure 33 includes a low-temperature GaN buffer layer 35, an n-type GaN layer 37, an active layer 39 of a quantum well structure, and a p-type gallium nitride based semiconductor layer 37. The p-type gallium nitride based semiconductor layer 37 includes, for example, a p-type AlGaN electron block layer and a p-type GaN contact layer. The primary surface 32a of the gallium oxide support base 32 is inclined at an angle of not less than 2 degrees and not more than 4 degrees relative to a (100) plane of monoclinic gallium oxide. Owing to this inclination, the gallium nitride based semiconductor epitaxially grown on the primary surface 32a of the gallium oxide support base has a flat surface.
摘要翻译： 提供了一种氮化镓基半导体器件，其包括在氧化镓晶片上设置有平坦c面的氮化镓基半导体膜。 发光二极管LED包括具有单斜氧化镓的主表面32a的氧化镓载体基底32和III族氮化物的叠层结构33。 层压结构33的半导体台面包括低温GaN缓冲层35，n型GaN层37，量子阱结构的有源层39和p型氮化镓基半导体层37. p 型氮化镓系半导体层37例如包括p型AlGaN电子阻挡层和p型GaN接触层。 氧化镓载体基体32的主表面32a相对于单斜晶系氧化镓的（100）面倾斜2度以上4度以下。 由于该倾斜，在氧化镓载体基体的主表面32a上外延生长的氮化镓基半导体具有平坦的表面。
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公开(公告)号：US08377204B2
公开(公告)日：2013-02-19
申请号：US12305001
申请日：2006-06-16
CPC分类号： C30B23/005 , C30B29/403 , C30B35/002 , Y10T428/2982
摘要： Affords methods of growing III nitride single crystals of favorable crystallinity with excellent reproducibility, and the III nitride crystals obtained by the growth methods. One method grows a III nitride single crystal (3) inside a crystal-growth vessel (11), the method being characterized in that a porous body formed from a metal carbide, whose porosity is between 0.1% and 70% is employed in at least a portion of the crystal-growth vessel (11). Employing the crystal-growth vessel (11) makes it possible to discharge from 1% to 50% of a source gas (4) inside the crystal-growth vessel (11) via the pores in the porous body to the outside of the crystal-growth vessel (11).
摘要翻译： 提供具有良好重现性的具有良好结晶度的III族氮化物单晶的方法和通过生长方法获得的III族氮化物晶体。 一种方法是在晶体生长容器（11）的内部生长III族氮化物单晶（3），其特征在于，至少使用由孔隙率在0.1％至70％之间的金属碳化物形成的多孔体 晶体生长容器（11）的一部分。 采用晶体生长容器（11）使得可以通过多孔体中的孔将晶体生长容器（11）内的源气体（4）的1％〜50％排出到晶体生长容器 生长容器（11）。
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