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11.发明授权Reducing the natural current limit in a power MOS device by reducing the gate-source voltage 失效通过降低栅源电压降低功率MOS器件的自然电流限制
公开(公告)号：US5579193A
公开(公告)日：1996-11-26
申请号：US486926
申请日：1995-06-07
IPC分类号： H03K17/082 , H02H7/10
CPC分类号： H03K17/0822
摘要： In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, sensing circuitry 30 to sense a predetermined trigger current, and limitation circuitry 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I.sub.D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I.sub.D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I.sub.D so that MOS device 110 is not damaged by the short circuit condition.
摘要翻译： 根据本发明，用于保护集成电路的功率MOS输出装置与过剩漏极电流的输出限流电路包括功率MOS器件110，检测电路30以感测预定的触发电流，以及限制电路20至 将MOS输出装置110上的栅极 - 源极电压降低到预定的大致固定值。 漏极电流ID响应于栅极 - 源极电压从输出端子102流过功率MOS器件110。 短路状态可允许过量的漏极电流ID流过输出端子102.响应于感测触发电流，栅极 - 源极电压被降低。 降低栅极 - 源极电压会提高MOS器件110的漏极 - 源极电阻并且减少漏极电流ID，使得MOS器件110不会被短路状态损坏。
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公开(公告)号：US06324044B1
公开(公告)日：2001-11-27
申请号：US09305571
申请日：1999-05-05
IPC分类号： H02H100
CPC分类号： G06F13/385
摘要： A controlled area network (CAN) driver provides improved symmetry between its differential output signals CAN-H and CAN-L, and provides protection for its low voltage devices from voltage transients occurring on its output lines. A plurality of CAN drivers 80 are serially interconnected to form a driver system, wherein each downstream driver stage receives a time-delayed form of the digital input signal TxD, each stage providing a time-delayed contribution to the differential output signals of the overall driver system.
摘要翻译： 控制区域网络（CAN）驱动器在其差分输出信号CAN-H和CAN-L之间提供改进的对称性，并为其低压器件提供对其输出线路上发生的电压瞬变的保护。 多个CAN驱动器80串联互连以形成驱动器系统，其中每个下游驱动器级接收时间延迟形式的数字输入信号TxD，每个级为整个驱动器的差分输出信号提供时间延迟的贡献 系统。
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13.发明授权Reducing the natural current limit in a power MOS device by reducing the gate-source voltage 失效通过降低栅源电压降低功率MOS器件的自然电流限制
公开(公告)号：US5541799A
公开(公告)日：1996-07-30
申请号：US265609
申请日：1994-06-24
IPC分类号： H03K17/082 , H02H7/10
CPC分类号： H03K17/0822
摘要： In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, a means 30 to sense a predetermined trigger current, and a means 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I.sub.D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I.sub.D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I.sub.D so that MOS device 110 is not damaged by the short circuit condition.
摘要翻译： 根据本发明，用于保护集成电路的功率MOS输出装置与过剩漏极电流的输出限流电路包括功率MOS器件110，感测预定触发电流的装置30和装置20至 将MOS输出装置110上的栅极 - 源极电压降低到预定的大致固定值。 漏极电流ID响应于栅极 - 源极电压从输出端子102流过功率MOS器件110。 短路状态可允许过量的漏极电流ID流过输出端子102.响应于感测触发电流，栅极 - 源极电压被降低。 降低栅极 - 源极电压会提高MOS器件110的漏极 - 源极电阻并且减少漏极电流ID，使得MOS器件110不会被短路状态损坏。
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公开(公告)号：US5408141A
公开(公告)日：1995-04-18
申请号：US160
申请日：1993-01-04
IPC分类号： H01L27/02 , H03K17/082 , H03K3/353
CPC分类号： H01L27/0248 , H03K17/0822
摘要： An integrated power device comprises a power transistor (26) and a plurality of sense transistors (38), (40), (42), (44), and (46). Sense transistors (38), (40), (42), and (44) are constructed around the periphery of the active area occupied by power transistor (26). Sense transistor (46) is located within the interior of the active area occupied by power transistor (26) and contact is made to the necessary source region (64) of transistor (46) using a second level of metal interconnect to form a source contact (74).
摘要翻译： 集成的功率器件包括功率晶体管（26）和多个感测晶体管（38），（40），（42），（44）和（46）。 感测晶体管（38），（40），（42）和（44）围绕由功率晶体管（26）占据的有源区域的外围构成。 感测晶体管（46）位于由功率晶体管（26）占据的有效区域的内部，并且使用第二级金属互连件与晶体管（46）的必要源极区域（64）接触以形成源极接触 （74）。
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公开(公告)号：US06236098B1
公开(公告)日：2001-05-22
申请号：US09061452
申请日：1998-04-16
IPC分类号： H01L31058
CPC分类号： H01L23/34 , H01L2224/05001 , H01L2224/05022 , H01L2224/05023 , H01L2224/05027 , H01L2224/05567 , H01L2224/05572 , H01L2224/13 , H01L2924/3011
摘要： An integrated circuit chip (10, 50, 100) may comprise an integrated circuit (14, 54, 108, 110, 112) formed in a semiconductor layer (12, 52, 102). A thermal contact (16, 56, 116) may be formed at a high temperature region of the integrated circuit (14, 54, 108, 110, 112). A thick plated metal layer (40, 80, 140) may be generally isolated from the integrated circuit (14, 54, 108, 110, 112). The thick plated metal layer (40, 80, 140) may include a base (42, 82, 142) and an exposed surface (44, 84, 144) opposite the base (42, 82, 142). The base (42, 82, 142) may be coupled to the thermal contact (16, 56, 116) to receive thermal energy of the high temperature region. The exposed surface (44, 84, 144) may dissipate thermal energy received by the thick plated metal layer (40, 80, 140).
摘要翻译： 集成电路芯片（10,50,100）可以包括形成在半导体层（12,52,102）中的集成电路（14,54,108,110,112）。 可以在集成电路（14,54,108,110,112）的高温区域形成热接触（16,56,116）。 厚电镀金属层（40,80,140）可以通常与集成电路（14,54,108,110,112）隔离。 厚电镀金属层（40,80,140）可以包括基部（42,82,142）和与基部（42,82,142）相对的暴露表面（44,84,144）。 基座（42,82,142）可以联接到热接触件（16,56,116）以接收高温区域的热能。 暴露表面（44,84,144）可以消散由厚镀金属层（40,80,140）接收的热能。
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公开(公告)号：US06486740B1
公开(公告)日：2002-11-26
申请号：US09651568
申请日：2000-08-28
IPC分类号： H03F114
CPC分类号： H03F1/14
摘要： One aspect of the invention is an integrated circuit (10 or 110) comprising an amplifier (11 or 111) having at least two poles in its frequency response and an output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) coupled to an output node (30) of the amplifier (11 or 111). The output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) is operable to create a feedback signal proportional to the impedance of an output load (50) coupled to the output node (30), and create a zero in the frequency response of the amplifier (11 or 111) in response to the feedback signal between the at least two poles.
摘要翻译： 本发明的一个方面是一种集成电路（10或110），包括在其频率响应中具有至少两个极的放大器（11或111）和输出阻抗补偿电路（M1A，M2，M3，AC1或M1A，M2， M3，M4，AC1）耦合到放大器（11或111）的输出节点（30）。 输出阻抗补偿电路（M1A，M2，M3，AC1或M1A，M2，M3，M4，AC1）可操作以产生与耦合到输出节点（30）的输出负载（50）的阻抗成比例的反馈信号， ，并且响应于至少两个极之间的反馈信号，在放大器（11或111）的频率响应中产生零。
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17.发明授权公开(公告)号：US06376870B1
公开(公告)日：2002-04-23
申请号：US09658202
申请日：2000-09-08
IPC分类号： H01L2972
CPC分类号： H01L21/823493 , H01L27/088 , H01L29/1087
摘要： A high-breakdown voltage transistor (30; 30′) is disclosed. The transistor (30; 30′) is formed into a well arrangement in which a shallow, heavily doped, well (44) is disposed at least partially within a deeper, more lightly-doped well (50), both formed into an epitaxial layer (43) of the substrate (42). The deep well (50) is also used, by itself, for the formation of high-voltage transistors, while the shallower well (44) is used by itself in low-voltage, high-performance transistors. This construction permits the use of high-performance, and precisely matching, transistors in high bias voltage applications, without fear of body-to-substrate (or “back-gate-to-substrate”) junction breakdown.
摘要翻译： 公开了一种高耐压晶体管（30; 30'）。 晶体管（30; 30'）形成为阱布置，其中浅的，重掺杂的阱（44）至少部分地设置在更深，更轻掺杂的阱（50）内，两者都形成为外延层 （42）的（43）。 深阱（50）本身也用于形成高压晶体管，而较浅的阱（44）本身用于低电压，高性能的晶体管。 这种结构允许在高偏压应用中使用高性能和精确匹配的晶体管，而不用担心体对衬底（或“背栅极到衬底”）结击穿。
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公开(公告)号：US06169309A
公开(公告)日：2001-01-02
申请号：US09159947
申请日：1998-09-24
IPC分类号： H01L2976
CPC分类号： H01L27/0251
摘要： A circuit for protecting a transistor against electrical transients. The circuit comprises a first diode coupled between a first terminal coupled to a power supply and a control terminal of the protected transistor. The circuit also comprises a second diode and a resistor coupling the control terminal of the protected transistor to a reference potential. A second transistor is coupled in shunt to the protected transistor. The voltage on the control terminal of the second transistor is determined by the current through the resistor. The embodiments may be implemented in an integrated circuit wherein the second, shunting transistor is formed from parasitic elements within the semiconductor body in which the protected transistor is formed. In one embodiment, the protected MOS transistor is formed in an n-well 504 and a shunting bipolar transistor is formed between the n-well 504 and an n-doped guard ring 500 formed adjacent to the n-well in the p-doped substrate 508.
摘要翻译： 用于保护晶体管免受电瞬态的电路。 电路包括耦合在耦合到电源的第一端子和受保护晶体管的控制端子之间的第一二极管。 该电路还包括将受保护晶体管的控制端耦合到参考电位的第二二极管和电阻器。 第二晶体管耦合到分流到保护晶体管。 第二晶体管的控制端子上的电压由通过电阻器的电流决定。 实施例可以在集成电路中实现，其中第二分流晶体管由形成有保护晶体管的半导体主体内的寄生元件形成。 在一个实施例中，被保护的MOS晶体管形成在n阱504中，并且分流双极晶体管形成在n阱504和邻近p掺杂衬底中的n阱附近形成的n掺杂保护环500之间 508。
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19.发明授权
公开(公告)号：US6144070A
公开(公告)日：2000-11-07
申请号：US141496
申请日：1998-08-28
IPC分类号： H01L23/60 , H01L27/02 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/78 , H01L29/76 , H01L23/58 , H01L23/62 , H01L29/94
CPC分类号： H01L29/7816 , H01L23/60 , H01L27/0262 , H01L29/0878 , H01L29/402 , H01L29/7393 , H01L29/7436 , H01L29/7813 , H01L2924/0002
摘要： A transistor including a source region 506 in a semiconductor body 502; a bulk region 508 in the semiconductor body adjacent the source region; a drain region in the semiconductor body adjacent the bulk region but opposite the source region, the drain region including doped regions 504,514 of n and p dopant types; and a field plate 516 formed over the semiconductor body adjacent the drain region between the drain region and the bulk region.
摘要翻译： 一种晶体管，包括半导体本体502中的源极区域506; 邻近源极区域的半导体本体区域508; 所述半导体本体中的漏极区域邻近所述体区域但与所述源极区域相对，所述漏极区域包括n和p掺杂剂类型的掺杂区域504,514; 以及形成在半导体本体上的与漏极区域和主体区域之间的漏极区域相邻的场板516。
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20.发明授权MOS ESD CDM clamp with integral substrate injection guardring and method for fabrication 有权具有集成衬底注入防护罩的MOS ESD CDM夹具及其制造方法公开(公告)号：US06940131B2
公开(公告)日：2005-09-06
申请号：US10609920
申请日：2003-06-30
IPC分类号： H01L27/02 , H01L29/06 , H01L29/423 , H01L23/62
CPC分类号： H01L29/0692 , H01L27/0266 , H01L29/4238
摘要： The present invention includes a MOS device (100) that has a P-type substrate (102) and an N-type drain region (104) formed within the substrate (102). An annular N-type source region (106) generally surrounds the drain region (104). The source region (106) serves as both the source for the MOS device (100) and a sacrificial collector guard ring for an electrostatic discharge protection circuit. An annular gate region (110) generally surrounds the drain region (104) and is electrically insulated from the drain region (104) and electrically connected to the source region (106). An annular P-type bulk region (108) generally surrounds the source region (106) and is electrically connected to the source region (106).
摘要翻译： 本发明包括具有形成在基板（102）内的P型基板（102）和N型漏极区（104）的MOS器件（100）。 环形N型源极区域（106）通常围绕漏极区域（104）。 源极区域（106）用作MOS器件（100）的源极和用于静电放电保护电路的牺牲集电极保护环。 环形栅极区域（110）通常围绕漏极区域（104）并且与漏极区域（104）电绝缘并且电连接到源极区域（106）。 环形P型体区域（108）通常围绕源极区域（106）并且电连接到源极区域（106）。
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