公开(公告)号：US10580723B2

公开(公告)日：2020-03-03

申请号：US16427172

申请日：2019-05-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Reynaldo Corpuz Javier ,  Alok Kumar Lohia ,  Andy Quang Tran

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L23/29 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31

Abstract: A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals.A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.

公开(公告)号：US10366947B2

公开(公告)日：2019-07-30

申请号：US15438533

申请日：2017-02-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Reynaldo Corpuz Javier ,  Alok Kumar Lohia ,  Andy Quang Tran

IPC: H01L21/44 ,  H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L23/29 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31

Abstract: A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.

公开(公告)号：US09608158B2

公开(公告)日：2017-03-28

申请号：US15336566

申请日：2016-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Andy Quang Tran ,  Lance Wright

IPC: H01L23/495 ,  H01L27/14 ,  H01L21/82 ,  H01L31/16 ,  H01L31/0232 ,  H01L31/08 ,  H01L31/02 ,  H01L31/09 ,  H01L31/101

CPC classification number: H01L31/16 ,  H01L21/82 ,  H01L25/165 ,  H01L25/167 ,  H01L27/14 ,  H01L31/02002 ,  H01L31/02325 ,  H01L31/08 ,  H01L31/09 ,  H01L31/101 ,  H01L31/18 ,  H01L33/54 ,  H01L33/58 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/1815 ,  H01L2933/0033 ,  H01L2933/005 ,  H01L2933/0058 ,  H01L2933/0066 ,  H01L2224/45099

Abstract: A method for fabricating a semiconductor proximity sensor includes providing a flat leadframe with a first and a second surface. The second surface is solderable. The leadframe includes a first and a second pad, a plurality of leads, and fingers framing the first pad. The fingers are spaced from the first pad by a gap which is filled with a clear molding compound. A light-emitting diode (LED) chip is assembled on the first pad and encapsulated by a first volume of the clear compound. The first volume outlined as a first lens. A sensor chip is assembled on the second pad and encapsulated by a second volume of the clear compound. The second volume outlined as a second lens. Opaque molding compound fills the space between the first and second volumes of clear compound and forms walls rising from the frame of fingers to create an enclosed cavity for the LED. The pads, leads, and fingers connected to a board using a layer of solder for attaching the proximity sensor.

公开(公告)号：US20170047469A1

公开(公告)日：2017-02-16

申请号：US15336566

申请日：2016-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Andy Quang Tran ,  Lance Wright

IPC: H01L31/16 ,  H01L31/08 ,  H01L31/02 ,  H01L31/0232

CPC classification number: H01L31/16 ,  H01L21/82 ,  H01L25/165 ,  H01L25/167 ,  H01L27/14 ,  H01L31/02002 ,  H01L31/02325 ,  H01L31/08 ,  H01L31/09 ,  H01L31/101 ,  H01L31/18 ,  H01L33/54 ,  H01L33/58 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/1815 ,  H01L2933/0033 ,  H01L2933/005 ,  H01L2933/0058 ,  H01L2933/0066 ,  H01L2224/45099

Abstract: A method for fabricating a semiconductor proximity sensor includes providing a flat leadframe with a first and a second surface. The second surface is solderable. The leadframe includes a first and a second pad, a plurality of leads, and fingers framing the first pad. The fingers are spaced from the first pad by a gap which is filled with a clear molding compound. A light-emitting diode (LED) chip is assembled on the first pad and encapsulated by a first volume of the clear compound. The first volume outlined as a first lens. A sensor chip is assembled on the second pad and encapsulated by a second volume of the clear compound. The second volume outlined as a second lens. Opaque molding compound fills the space between the first and second volumes of clear compound and forms walls rising from the frame of fingers to create an enclosed cavity for the LED. The pads, leads, and fingers connected to a board using a layer of solder for attaching the proximity sensor.

Abstract translation: 制造半导体接近传感器的方法包括提供具有第一表面和第二表面的扁平引线框架。 第二个表面是可焊接的。 引线框架包括第一和第二焊盘，多个引线和构成第一焊盘的指状物。 指状物通过填充有透明模塑料的间隙与第一垫片隔开。 发光二极管（LED）芯片组装在第一焊盘上并由第一体积的透明化合物封装。 第一卷被列为第一个镜头。 传感器芯片组装在第二焊盘上并被第二体积的透明化合物封装。 第二卷被列为第二个镜头。 不透明的模塑料填充第一和第二体积的透明化合物之间的空间并且形成从手指框架上升的壁以产生用于LED的封闭空腔。 焊盘，引线和手指连接到板上，使用焊料层来附接接近传感器。

公开(公告)号：US20150262903A1

公开(公告)日：2015-09-17

申请号：US14215896

申请日：2014-03-17

Applicant: Texas Instruments Incorporated

Inventor： Alok Kumar Lohia ,  Reynaldo Corpuz Javier ,  Andy Quang Tran

IPC: H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L21/48 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L23/3107 ,  H01L21/4842 ,  H01L21/56 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49565 ,  H01L23/49838 ,  H01L24/97 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/10254 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2224/85

Abstract: A semiconductor device has a leadframe with a pad and a row of elongated leads with a solderable surfaces in a common plane; a package encapsulating the leadframe with an assembled semiconductor device, leaving the common-plane lead surfaces un-encapsulated and coplanar with the package material between adjacent leads, the row of aligned leads positioned along a package edge; and grooves in the package material cut in the common-plane surface, the grooves extend along a portion of each lead length, have a width and a depth about twice the width, and expose solderable lead surfaces.

Abstract translation: 半导体器件具有引线框架，其具有焊盘和一排具有可焊接表面在公共平面中的细长引线; 封装引线框架与组装的半导体器件的封装，使公共平面引线表面与相邻引线之间的封装材料未封装和共面，沿着封装边缘定位一排排列的引线; 并且在共同平面表面中切割的封装材料中的凹槽沿着每个引线长度的一部分延伸，具有宽度和宽度的两倍，并且暴露可焊接的引线表面。

公开(公告)号：US20220092767A1

公开(公告)日：2022-03-24

申请号：US17544896

申请日：2021-12-07

Applicant: Texas Instruments Incorporated

Inventor： Reynaldo Corpuz Javier ,  Alok Kumar Lohia ,  Andy Quang Tran

IPC: G06T7/00 ,  H01L23/495 ,  H01L23/00

Abstract: An IC assembly including an exposed pad integrated circuit (“IC”) package having a thermal pad with a top surface and a bottom surface and with at least one peripheral surface portion extending transversely of and continuous with the bottom surface. The bottom surface and the at least one peripheral surface are exposed through a layer of mold compound. Also, methods of making an exposed pad integrated circuit (“IC”) package assembly. One method includes optically inspecting a solder bond bonding a thermal pad of an exposed pad IC package to a printed circuit board. Another method includes wave soldering an exposed pad of an IC package to a printed circuit board.

公开(公告)号：US09768098B2

公开(公告)日：2017-09-19

申请号：US15099864

申请日：2016-04-15

Applicant: Texas Instruments Incorporated

Inventor： Alok Kumar Lohia ,  Reynaldo Corpuz Javier ,  Andy Quang Tran

IPC: H01L23/495 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L29/06 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/4952 ,  H01L21/4825 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/85 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor device comprising a stack of semiconductor chips. The semiconductor chips have an electrically active side and an opposite electrically inactive side. The active sides bordered by an edge having first lengths and the inactive sides bordered by a parallel edge having a second lengths smaller than the first lengths. A substrate has an assembly pad bordered by a linear edge having a third length equal to or smaller than the first lengths. The inactive chip side attached to the pad so that the edge of the first lengths are parallel to the edge of the third length. The active side of the attached chip forms an overhang over the pad, when the third length is smaller than the first lengths.

公开(公告)号：US20160286652A1

公开(公告)日：2016-09-29

申请号：US14671727

申请日：2015-03-27

Applicant: Texas Instruments Incorporated

Inventor： Reynaldo Corpuz Javier ,  Alok Kumar Lohia ,  Andy Quang Tran

IPC: H05K1/18 ,  G06T7/00 ,  H04N7/18 ,  H05K3/30

CPC classification number: G06T7/0008 ,  H01L22/12 ,  H01L23/49503 ,  H01L23/49555 ,  H01L23/49568 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/3421 ,  H05K2201/10689 ,  H05K2201/10969 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: An IC assembly including an exposed pad integrated circuit (“IC”) package having a thermal pad with a top surface and a bottom surface and with at least one peripheral surface portion extending transversely of and continuous with the bottom surface. The bottom surface and the at least one peripheral surface are exposed through a layer of mold compound. Also, methods of making an exposed pad integrated circuit (“IC”) package assembly. One method includes optically inspecting a solder bond bonding a thermal pad of an exposed pad IC package to a printed circuit board. Another method includes wave soldering an exposed pad of an IC package to a printed circuit board.

Abstract translation: 一种IC组件，其包括具有顶表面和底表面的热垫的暴露焊盘集成电路（“IC”）封装，以及至少一个横向并与底表面连续延伸的外围表面部分。 底表面和至少一个外围表面通过一层模具化合物暴露。 另外，制造裸露集成电路（“IC”）封装组件的方法。 一种方法包括光学检查焊接接合将暴露的焊盘IC封装的散热焊盘接合到印刷电路板。 另一种方法包括将IC封装的裸露焊盘波峰焊到印刷电路板上。

公开(公告)号：US20160233147A1

公开(公告)日：2016-08-11

申请号：US15099864

申请日：2016-04-15

Applicant: Texas Instruments Incorporated

Inventor： Alok Kumar Lohia ,  Reynaldo Corpuz Javier ,  Andy Quang Tran

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/4952 ,  H01L21/4825 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/85 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor device comprising a stack of semiconductor chips. The semiconductor chips have an electrically active side and an opposite electrically inactive side. The active sides bordered by an edge having first lengths and the inactive sides bordered by a parallel edge having a second lengths smaller than the first lengths. A substrate has an assembly pad bordered by a linear edge having a third length equal to or smaller than the first lengths. The inactive chip side attached to the pad so that the edge of the first lengths are parallel to the edge of the third length. The active side of the attached chip forms an overhang over the pad, when the third length is smaller than the first lengths.

Abstract translation: 一种包括半导体芯片堆叠的半导体器件。 半导体芯片具有电活动侧和相反的电不活动侧。 由具有第一长度的边缘接合的主动侧和由具有小于第一长度的第二长度的平行边缘接合的非活动侧。 衬底具有由具有等于或小于第一长度的第三长度的线性边缘界定的组装垫。 不活动的芯片侧附接到焊盘，使得第一长度的边缘平行于第三长度的边缘。 当第三长度小于第一长度时，附接芯片的活动侧在焊盘上形成突出部。

公开(公告)号：US20160005712A1

公开(公告)日：2016-01-07

申请号：US14854886

申请日：2015-09-15

Applicant: Texas Instruments Incorporated

Inventor： Andy Quang Tran ,  Reynaldo Corpuz Javier ,  Alok Kumar Lohia

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L24/97 ,  H01L21/4825 ,  H01L21/4835 ,  H01L21/4842 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49555 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/95 ,  H01L2224/432 ,  H01L2224/48091 ,  H01L2224/48096 ,  H01L2224/48106 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1711 ,  H01L2924/1715 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/48095

Abstract: A method for fabricating a semiconductor device package provides a metallic leadframes with a plurality of device sites. Each site including a pad and a plurality of leads with solderable surfaces. At least one set of leads are aligned in a row and are connected by rails to respective leads of an adjacent site. The leads and rails of the row having a surface in a common plane. The strip with the assembled sites and connecting rails are encapsulated in a packaging material, leaving the common-plane lead and rail surfaces un-encapsulated. Trenches are cut between adjacent sites by removing packaging material until reaching the rails. Thus, creating sidewalls of device packages connected by rails. Device packages are singulated from the strip by severing the connecting rails between adjacent sites in approximate halves, leaving a respective rail half as a straight protrusion attached to each lead. The protrusions are bent at an angle away from the common plane towards the package sidewall.

Abstract translation: 一种用于制造半导体器件封装的方法提供具有多个器件位置的金属引线框架。 每个场地包括一个焊盘和多个具有可焊接表面的引线。 至少一组引线被排列成一排，并且通过导轨连接到相邻位置的相应引线。 行的引线和轨道具有在公共平面中的表面。 具有组装位置和连接轨道的条带被封装在包装材料中，使共平面的引线和导轨表面未被封装。 通过移除包装材料直到到达轨道，在相邻位置之间切割沟槽。 因此，创建通过轨道连接的设备包的侧壁。 通过将相邻位置之间的连接轨道切割成近似一半，从条带中切割设备封装，留下相应的轨道半部，作为连接到每个引线的直的突起。 突起以与公共平面成一定角度朝向封装侧壁弯曲。