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31 条记录 (耗时 0.032 秒)

    Integrateable capacitors and microcoils and methods of making thereof
    11.
    发明申请
    Integrateable capacitors and microcoils and methods of making thereof 有权
    可集成电容器和微型线圈及其制造方法

    公开(公告)号：US20070148895A1

    公开(公告)日：2007-06-28

    申请号：US11319075

    申请日：2005-12-28

    申请人： Koenraad Van Schuylenbergh ,  Eugene Chow ,  JengPing Lu

    发明人： Koenraad Van Schuylenbergh ,  Eugene Chow ,  JengPing Lu

    IPC分类号： H01L21/00

    CPC分类号： H01G5/18 ,  H01F17/0006 ,  H01F17/02 ,  H01F21/04 ,  H01F27/40 ,  H01F41/041 ,  H01L28/10 ,  H01L28/40

    摘要： Methods for integrally forming high Q tunable capacitors and high Q inductors on a substrate are described. A method for integrally forming a capacitor and a microcoil on a substrate may involve depositing and patterning a dielectric layer on the substrate, depositing and patterning a sacrificial layer on the substrate, depositing and patterning conductive material on the semiconductor substrate, depositing and patterning a polymer layer on the semiconductor substrate, removing an exposed portion of the conductive material exposed by the patterned polymer layer to release a portion of the conductive pattern from the semiconductor substrate to form out-of-plane windings of the microcoil, depositing second conductive material on exposed portions of the conductive material, and removing the sacrificial layer. The patterned conductive material may include a windings portion of the microcoil, an overlapping electrode portion of the capacitor and a support portion for the electrode of the capacitor.

    摘要翻译： 描述了在衬底上整体形成高Q可调谐电容器和高Q电感器的方法。 用于在基板上一体地形成电容器和微线圈的方法可以包括在基板上沉积和图案化电介质层，在衬底上沉积和图案化牺牲层，在半导体衬底上沉积和图案化导电材料，沉积和图案化聚合物 去除由所述图案化聚合物层暴露的所述导电材料的暴露部分，以从所述半导体衬底释放所述导电图案的一部分，以形成所述微线圈的面外绕组，将第二导电材料沉积在暴露的 部分导电材料，并去除牺牲层。 图案化导电材料可以包括微线圈的绕组部分，电容器的重叠电极部分和用于电容器电极的支撑部分。

    Xerographic micro-assembler
    12.
    发明申请
    Xerographic micro-assembler 有权
    静电复印机

    公开(公告)号：US20060128057A1

    公开(公告)日：2006-06-15

    申请号：US11011652

    申请日：2004-12-14

    申请人： Jeng Lu ,  Eugene Chow

    发明人： Jeng Lu ,  Eugene Chow

    IPC分类号： H01L21/50 ,  H01L21/30 ,  B23P21/00

    CPC分类号： H01L25/50 ,  H01L21/67271 ,  H01L21/67282 ,  H01L21/67294 ,  H01L24/95 ,  H01L2224/95085 ,  H01L2224/95144 ,  H01L2224/95145 ,  H01L2924/14 ,  H01L2924/1461 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/53004 ,  Y10T29/5313 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53278 ,  H01L2924/00

    摘要： Xerographic micro-assembler systems and methods are disclosed. The systems and methods involve manipulating charge-encoded micro-objects. The charge encoding identifies each micro-object and specifies its orientation for sorting. The micro-objects are sorted in a sorting unit so that they have defined positions and orientations. The sorting unit has the capability of electrostatically and magnetically manipulating the micro-objects based on their select charge encoding. The sorted micro-objects are provided to an image transfer unit. The image transfer unit is adapted to receive the sorted micro-objects, maintain them in their sorted order and orientation, and deliver them to a substrate. Maintaining the sorted order as the micro-objects are delivered to the substrate may be accomplished through the use of an electrostatic image, as is done in xerography. The substrate with the micro-objects is further processed to interconnect the micro-objects—through electrical wiring, for example—to form the final micro-assembly.

    摘要翻译： 公开了静电印刷微组装系统和方法。 系统和方法涉及操纵电荷编码的微物体。 电荷编码识别每个微物体并指定其排列方向。 微物体在分类单元中排序，使得它们具有定义的位置和取向。 分选单元具有基于其选择电荷编码的静电和磁性操纵微物体的能力。 分类的微物体被提供给图像传送单元。 图像传送单元适于接收分类的微物体，将它们保持在排列顺序和方位，并将其传送到基底。 将排序的顺序作为微物体传送到基底可以通过使用静电图像来实现，如在静电复印中所做的那样。 具有微物体的衬底被进一步处理以使例如微通孔电线互连，以形成最终的微组件。

    Curved spring structure with elongated section located under cantilevered section
    13.
    发明申请
    Curved spring structure with elongated section located under cantilevered section 有权
    弯曲弹簧结构，细长部分位于悬臂部分下方

    公开(公告)号：US20060087335A1

    公开(公告)日：2006-04-27

    申请号：US10971467

    申请日：2004-10-21

    申请人： Thomas Hantschel ,  Eugene Chow

    发明人： Thomas Hantschel ,  Eugene Chow

    IPC分类号： G01R31/02

    CPC分类号： H01G5/18 ,  G01R1/06738

    摘要： A curved spring structure includes a base section extending parallel to the substrate surface, a curved cantilever section bent away from the substrate surface, and an elongated section extending from the base section along the substrate surface under the cantilevered section. The spring structure includes a spring finger formed from a self-bending material film (e.g., stress-engineered metal, bimorph/bimetallic) that is patterned and released. A cladding layer is then electroplated and/or electroless plated onto the spring finger for strength. The elongated section is formed from plating material deposited simultaneously with cladding layers. To promote the formation of the elongated section, a cementation layer is provided under the spring finger to facilitate electroplating, or the substrate surface is pre-treated to facilitate electroless plating.

    摘要翻译： 弯曲弹簧结构包括平行于基板表面延伸的基部部分，弯曲的远离基板表面的弯曲悬臂部分，以及从基部沿着悬臂部分下方的基板表面延伸的细长部分。 弹簧结构包括由图案化和释放的自弯曲材料膜（例如，应力工程金属，双晶型/双金属）形成的弹簧指状物。 然后将包覆层电镀和/或无电镀在弹簧手指上用于强度。 细长部分由与包覆层同时沉积的电镀材料形成。 为了促进细长部分的形成，在弹簧指状物下方设置有胶结层以促进电镀，或者基板表面被预处理以便于化学镀。

    Pattern-print thin-film transistors with top gate geometry
    14.
    发明授权
    Pattern-print thin-film transistors with top gate geometry 有权
    具有顶栅几何形状的图案印刷薄膜晶体管

    公开(公告)号：US07884361B2

    公开(公告)日：2011-02-08

    申请号：US12817127

    申请日：2010-06-16

    申请人： William Wong ,  Rene Lujan ,  Eugene Chow

    发明人： William Wong ,  Rene Lujan ,  Eugene Chow

    IPC分类号： H01L21/00

    CPC分类号： H01L29/41733 ,  H01L27/124 ,  H01L27/1285 ,  H01L27/1288 ,  H01L27/1292 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757

    摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.

    摘要翻译： 公开了一种自对准薄膜顶栅晶体管及其制造方法。 通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。 然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。 在其上形成半导体层和绝缘层。 然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。 在感光材料的显影之后，沉积栅极金属层。 然后再次通过数字光刻法在器件上形成第二印刷图案掩模。 蚀刻和去除感光材料离开自对准顶栅电极。

    Patterned-print thin-film transistors with top gate geometry
    15.
    发明申请
    Patterned-print thin-film transistors with top gate geometry 有权
    具有顶栅几何形状的图案印刷薄膜晶体管

    公开(公告)号：US20070026585A1

    公开(公告)日：2007-02-01

    申请号：US11193847

    申请日：2005-07-28

    申请人： William Wong ,  Rene Lujan ,  Eugene Chow

    发明人： William Wong ,  Rene Lujan ,  Eugene Chow

    IPC分类号： H01L21/84

    CPC分类号： H01L29/41733 ,  H01L27/124 ,  H01L27/1285 ,  H01L27/1288 ,  H01L27/1292 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757

    摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.

    摘要翻译： 公开了一种自对准薄膜顶栅晶体管及其制造方法。 通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。 然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。 在其上形成半导体层和绝缘层。 然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。 在感光材料的显影之后，沉积栅极金属层。 然后再次通过数字光刻法在器件上形成第二印刷图案掩模。 蚀刻和去除感光材料离开自对准顶栅电极。

    Method Of Producing Microsprings Having Nanowire Tip Structures
    17.
    发明申请
    Method Of Producing Microsprings Having Nanowire Tip Structures 审中-公开
    具有纳米线尖端结构的微管生产方法

    公开(公告)号：US20110163061A1

    公开(公告)日：2011-07-07

    申请号：US13044933

    申请日：2011-03-10

    申请人： Eugene Chow ,  Pengfei Qi

    发明人： Eugene Chow ,  Pengfei Qi

    IPC分类号： C03C25/68 ,  B05D1/32 ,  B82Y40/00

    CPC分类号： B81C1/0015 ,  B81B2203/019 ,  B81B2207/07 ,  B82Y10/00

    摘要： A stress-engineered microspring is formed generally in the plane of a substrate. A nanowire (or equivalently, a nanotube) is formed at the tip thereof, also in the plane of the substrate. Once formed, the length of the nanowire may be defined, for example photolithographically. A sacrificial layer underlying the microspring may then be removed, allowing the engineered stresses in the microspring to cause the structure to bend out of plane, elevating the nanowire off the substrate and out of plane. Use of the nanowire as a contact is thereby provided. The nanowire may be clamped at the tip of the microspring for added robustness. The nanowire may be coated during the formation process to provide additional functionality of the final device.

    摘要翻译： 应力工程微球通常在基底的平面上形成。 纳米线（或等效地，纳米管）也在其顶端形成在基板的平面中。 一旦形成，可以例如光刻地限定纳米线的长度。 然后可以去除位于微弹簧下面的牺牲层，允许微弹簧中的工程应力使结构弯曲出平面，从而使纳米线离开基底并离开平面。 由此提供了使用纳米线作为接触。 可以将纳米线夹在微弹簧的末端以增加坚固性。 在形成过程中可以涂覆纳米线以提供最终装置的附加功能。

    Method of manufacturing fine features for thin film transistors
    18.
    发明申请
    Method of manufacturing fine features for thin film transistors 有权
    制造薄膜晶体管精细特征的方法

    公开(公告)号：US20070221611A1

    公开(公告)日：2007-09-27

    申请号：US11388731

    申请日：2006-03-24

    申请人： Eugene Chow ,  William Wong ,  Michael Chabinyc ,  Ana Arias

    发明人： Eugene Chow ,  William Wong ,  Michael Chabinyc ,  Ana Arias

    IPC分类号： H01B13/00 ,  C23F1/00

    CPC分类号： H01L29/4908 ,  H01L27/124 ,  H01L27/1292

    摘要： A process for fabricating fine features such as small gate electrodes on a transistor. The process involves the jet-printing of a mask and the plating of a metal to fabricate sub-pixel and standard pixel size features in one layer. Printing creates a small sub-pixel size gap mask for plating a fine feature. A second printed mask may be used to protect the newly formed gate and etch standard pixel size lines connecting the small gates.

    摘要翻译： 一种在晶体管上制造诸如小栅电极的精细特征的工艺。 该方法涉及一种掩模的喷墨印刷和金属镀层，以在一层中制造亚像素和标准像素尺寸特征。 打印创建一个小的子像素大小的间隙掩模，用于电镀精细特征。 可以使用第二印刷掩模来保护新形成的栅极并蚀刻连接小栅极的标准像素尺寸线。