公开(公告)号：US20210296291A1

公开(公告)日：2021-09-23

申请号：US16846429

申请日：2020-04-13

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang ,  Cheng-Ta Ko

IPC: H01L25/075 ,  H01L33/62 ,  H01L33/52 ,  H01L33/00

Abstract: A manufacturing method of chip package structure includes following steps. A carrier is provided. A first patterned circuit layer and a first dielectric layer covering the first patterned circuit layer have been formed on the carrier. A flat structure layer is formed on the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and covers the flat structure layer and a portion of the first dielectric layer. A second patterned circuit layer is formed on the second dielectric layer. The second patterned circuit layer includes a plurality of pads. An orthographic projection of the flat structure layer on the carrier overlaps orthographic projections of the pads on the carrier. A plurality of chips are disposed on the pads. A molding compound is formed to cover the second dielectric layer and encapsulate the chips and the pads.

公开(公告)号：US12062742B2

公开(公告)日：2024-08-13

申请号：US17653659

申请日：2022-03-07

Applicant: Unimicron Technology Corp.

Inventor： Hao-Wei Tseng ,  Chi-Hai Kuo ,  Jeng-Ting Li ,  Ying-Chu Chen ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L33/54 ,  H01L23/00 ,  H01L25/075

CPC classification number: H01L33/54 ,  H01L24/83 ,  H01L25/0753 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/29194 ,  H01L2224/32227 ,  H01L2224/83099 ,  H01L2224/83203 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/8389 ,  H01L2924/12041 ,  H01L2933/005

Abstract: A package structure includes a substrate, a plurality of conductive pads, a light-emitting diode, a photo imageable dielectric material, and a black matrix. The substrate includes a top surface. The conductive pads are located on the top surface of the substrate. The light-emitting diode is located on the conductive pads. The photo imageable dielectric material is located between the light-emitting diode and the top surface of the substrate and between the conductive pads. An orthogonal projection of the light-emitting diode on the substrate is overlapped with an orthogonal projection of the photo imageable dielectric material on the substrate. The black matrix is located on the top surface of the substrate and the conductive pads.

公开(公告)号：US11764344B2

公开(公告)日：2023-09-19

申请号：US17209110

申请日：2021-03-22

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang

IPC: H01L33/62 ,  H01L33/06 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L33/54

CPC classification number: H01L33/06 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5386 ,  H01L33/54 ,  H01L2221/6835 ,  H01L2933/005 ,  H01L2933/0066

Abstract: A manufacturing method of a package structure is provided, which includes the following steps. A carrier having a surface is provided. A copper foil layer is laminated on the surface of the carrier. A subtractive process is performed on the copper foil layer to form a copper foil circuit layer on the carrier. The copper foil circuit layer exposes a part of the surface of the carrier. A build-up structure layer is formed on the copper foil circuit layer and the surface of the carrier. A first surface of the copper foil circuit layer is aligned with a second surface of the build-up structure layer. At least one electronic component is disposed on the build-up structure layer. A package colloid is formed to cover the electronic component and the build-up structure layer. The carrier is removed to expose the first surface of the copper foil circuit layer.

公开(公告)号：US20220328387A1

公开(公告)日：2022-10-13

申请号：US17232128

申请日：2021-04-15

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chi-Hai Kuo ,  Chia-Yu Peng ,  Tzyy-Jang Tseng

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683

Abstract: A package carrier includes a first redistribution layer having a first upper surface and a first lower surface and including a plurality of first redistribution circuits, a plurality of conductive through holes, a plurality of photoimageable dielectric layers, and a plurality of chip pads and a second redistribution layer disposed on the first upper surface of the first redistribution layer. The second redistribution layer has a second upper surface and a second lower surface aligned with and directly connected to the first upper surface of the first redistribution layer and includes a plurality of second redistribution circuits, a plurality of conductive structures, a plurality of Ajinomoto build-up Film (ABF) layers, and a plurality of solder ball pads. A line width and a line pitch of each of the first redistribution circuits are smaller than a line width and a line pitch of each of the second redistribution circuits.

公开(公告)号：US20220271208A1

公开(公告)日：2022-08-25

申请号：US17227391

申请日：2021-04-12

Applicant: Unimicron Technology Corp.

Inventor： Jeng-Ting Li ,  Chi-Hai Kuo ,  Cheng-Ta Ko ,  Pu-Ju Lin

IPC: H01L33/62 ,  H01L27/15 ,  H01L33/00

Abstract: A light emitting diode (LED) package structure includes a glass substrate, conductive through holes, active elements, an insulating layer, LEDs and pads. The glass substrate has an upper surface and a lower surface. The conductive through holes penetrate the glass substrate and connect the upper and the lower surfaces. The active elements are disposed on the upper surface of the glass substrate and electrically connected to the conductive through holes. The insulating layer is disposed on the upper surface and covers the active elements. The LEDs are disposed on the insulating layer and electrically connected to at least one of the active elements. The pads are disposed on the lower surface of the glass substrate and electrically connected to the conductive through holes. A source of at least one active elements is directly electrically connected to at least one of the corresponding pads through the corresponding conductive through hole.

公开(公告)号：US20210251107A1

公开(公告)日：2021-08-12

申请号：US17017702

申请日：2020-09-11

Applicant: Unimicron Technology Corp.

Inventor： Ra-Min Tain ,  Pu-Ju Lin ,  Cheng-Chung Lo ,  Chi-Hai Kuo ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng ,  John Hon-Shing Lau

IPC: H05K7/20 ,  F28D15/02 ,  F28D15/04 ,  B21D53/08

Abstract: A vapor chamber structure includes a thermally conductive housing, a capillary structure layer, a grid structure layer, and a working fluid. The thermally conductive housing has a sealed chamber, where a pressure in the sealed chamber is lower than a standard atmospheric pressure. The capillary structure layer is disposed in the sealed chamber. The grid structure layer is disposed in the sealed chamber and arranged along a first direction. A size of the grid structure layer is less than or equal to a size of the capillary structure layer. The working fluid fills the sealed chamber.

公开(公告)号：US11665832B2

公开(公告)日：2023-05-30

申请号：US17234805

申请日：2021-04-20

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang ,  Chia-Yu Peng ,  Shao-Chien Lee ,  Tzyy-Jang Tseng

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11 ,  H05K1/14 ,  H05K1/16 ,  H05K1/18 ,  H05K3/20 ,  H05K3/36 ,  H05K3/38 ,  H05K3/40 ,  H05K3/46 ,  H05K3/02

CPC classification number: H05K3/46 ,  H05K3/022 ,  H05K3/386 ,  H05K3/4038

Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.

公开(公告)号：US20230067112A1

公开(公告)日：2023-03-02

申请号：US17983396

申请日：2022-11-09

Applicant: Unimicron Technology Corp.

Inventor： Ra-Min Tain ,  John Hon-Shing Lau ,  Pu-Ju Lin ,  Wei-Ci Ye ,  Chi-Hai Kuo ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng

IPC: F28D15/04 ,  F28D15/02 ,  F28F3/10 ,  B23P15/26 ,  F28F21/08

Abstract: A vapor chamber structure includes a thermally conductive shell, a capillary structure layer, and a working fluid. The thermally conductive shell includes a first thermally conductive portion and a second thermally conductive portion. The first thermally conductive portion and the second thermally conductive portion are a thermally conductive plate that is integrally formed, and the thermally conductive shell is formed by folding the thermally conductive plate in half and then sealing the thermally conductive plate. The first thermally conductive portion has at least one first cavity, the second thermally conductive portion has at least one second cavity. At least one sealed chamber is defined between the thermally conductive plate, the first cavity and the second cavity. A pressure in the sealed chamber is lower than a standard atmospheric pressure. The capillary structure layer covers an inner wall of the sealed chamber. The working fluid is filled in the sealed chamber.

公开(公告)号：US11476234B2

公开(公告)日：2022-10-18

申请号：US16846429

申请日：2020-04-13

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang ,  Cheng-Ta Ko

IPC: H01L25/075 ,  H01L33/62 ,  H01L33/00 ,  H01L33/52

Abstract: A manufacturing method of chip package structure includes following steps. A carrier is provided. A first patterned circuit layer and a first dielectric layer covering the first patterned circuit layer have been formed on the carrier. A flat structure layer is formed on the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and covers the flat structure layer and a portion of the first dielectric layer. A second patterned circuit layer is formed on the second dielectric layer. The second patterned circuit layer includes a plurality of pads. An orthographic projection of the flat structure layer on the carrier overlaps orthographic projections of the pads on the carrier. A plurality of chips are disposed on the pads. A molding compound is formed to cover the second dielectric layer and encapsulate the chips and the pads.

公开(公告)号：US11460255B2

公开(公告)日：2022-10-04

申请号：US17113332

申请日：2020-12-07

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Pu-Ju Lin ,  Ying-Chu Chen ,  Wei-Ci Ye ,  Chi-Hai Kuo ,  Cheng-Ta Ko

IPC: B23P15/26 ,  F28D15/04 ,  C23F17/00 ,  H05K7/20 ,  H01L23/427

Abstract: A vapor chamber device and a manufacturing method are disclosed. The vapor chamber has a housing and multiple independent chambers. The housing includes two shells opposite to each other. The independent chambers are formed between the two shells. Each independent chamber contains a working fluid and has at least one diversion bump and a capillary structure. The diversion bump is formed on an inner surface of the second shell, and the capillary structure is mounted on the diversion bump. When the vapor chamber device is vertically mounted to a heat source, the independent chambers at an upper portion of the vapor chamber device still contain the working fluid. The working fluid in the independent chambers may not all flow to a bottom of the vapor chamber device. Therefore, a contact area between the working fluid and the heat source is increased and heat dissipation efficiency is improved.