公开(公告)号：US10818616B2

公开(公告)日：2020-10-27

申请号：US16361880

申请日：2019-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chu-Fu Lin ,  Ming-Tse Lin

IPC: H01L23/64 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.

公开(公告)号：US09437491B2

公开(公告)日：2016-09-06

申请号：US14791265

申请日：2015-07-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Tse Lin ,  Chu-Fu Lin ,  Chien-Li Kuo ,  Yung-Chang Lin

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/522 ,  H01L21/283 ,  H01L21/302 ,  H01L49/02

CPC classification number: H01L21/76898 ,  H01L21/283 ,  H01L21/302 ,  H01L21/7685 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/16 ,  H01L28/60 ,  H01L2224/02317 ,  H01L2224/0401 ,  H01L2224/4824 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.

Abstract translation: 本发明提供一种用TSV电极形成芯片的方法。 提供具有第一表面和第二表面的基底。 从第二表面的一侧进行变薄处理，使得第二表面变成第三表面。 接下来，在衬底中形成穿过第一表面和第三表面的穿透。 图案化材料层形成在衬底上，其中图案化材料层具有开口以暴露穿透通孔。 导电层形成在第三表面上，从而同时在穿透孔中形成TSV电极和开口中的表面导电层。

公开(公告)号：US09123789B2

公开(公告)日：2015-09-01

申请号：US13747492

申请日：2013-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Tse Lin ,  Chu-Fu Lin ,  Chien-Li Kuo ,  Yung-Chang Lin

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L21/76898 ,  H01L21/283 ,  H01L21/302 ,  H01L21/7685 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/16 ,  H01L28/60 ,  H01L2224/02317 ,  H01L2224/0401 ,  H01L2224/4824 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.

Abstract translation: 本发明提供一种用TSV电极形成芯片的方法。 提供具有第一表面和第二表面的基底。 从第二表面的一侧进行变薄处理，使得第二表面变成第三表面。 接下来，在衬底中形成穿过第一表面和第三表面的穿透。 图案化材料层形成在衬底上，其中图案化材料层具有开口以暴露穿透通孔。 导电层形成在第三表面上，从而同时在穿透孔中形成TSV电极和开口中的表面导电层。

公开(公告)号：US20240429093A1

公开(公告)日：2024-12-26

申请号：US18224576

申请日：2023-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ting Lin ,  Kai-Kuang Ho ,  Chuan-Lan Lin ,  Yu-Ping Wang ,  Chu-Fu Lin ,  Yi-Feng Hsu ,  Yu-Jie Lin

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/784 ,  H01L23/544

Abstract: A method for fabricating a semiconductor device includes the steps of first defining a scribe line on a front side of a wafer, in which the wafer includes an inter-metal dielectric (IMD) layer disposed on a substrate and an alternating stack disposed on the IMD layer. Next, part of the alternating stack is removed to form a trench on the front side of the wafer, a dielectric layer is formed in the trench, and then a dicing process is performed along the scribe line from a back side of the wafer to divide the wafer into chips.

公开(公告)号：US11646343B2

公开(公告)日：2023-05-09

申请号：US17136075

申请日：2020-12-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Teng-Chuan Hu ,  Chu-Fu Lin ,  Chun-Hung Chen

IPC: H01L49/02

CPC classification number: H01L28/91

Abstract: A capacitor structure comprises a substrate having a first side and a second side opposite to the first side; a plurality of first trenches formed on the first side of the substrate; a plurality of second trenches formed on the second side of the substrate; a first capacitor extending along the first side and into the first trenches; and a second capacitor extending along the second side and into the second trenches.

公开(公告)号：US20210005559A1

公开(公告)日：2021-01-07

申请号：US17023967

申请日：2020-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chu-Fu Lin ,  Ming-Tse Lin

IPC: H01L23/64 ,  H01L23/31

Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.

公开(公告)号：US10192808B1

公开(公告)日：2019-01-29

申请号：US15642349

申请日：2017-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Teng-Chuan Hu ,  Chun-Hung Chen ,  Chu-Fu Lin ,  Chun-Ting Yeh ,  Chung-Hsing Kuo ,  Ming-Tse Lin

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L21/321

Abstract: A semiconductor structure includes a substrate having a frontside surface and a backside surface. A through-substrate via extends into the substrate from the frontside surface. The through-substrate via comprises a top surface. A metal cap covers the top surface of the through-substrate via. A plurality of cylindrical dielectric plugs is embedded in the metal cap. The cylindrical dielectric plugs are distributed only within a central area of the metal cap. The central area is not greater than a surface area of the top surface of the through-substrate via.

公开(公告)号：US20160064300A1

公开(公告)日：2016-03-03

申请号：US14521893

申请日：2014-10-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chu-Fu Lin ,  Chien-Li Kuo ,  Kuo-Ming Chen

IPC: H01L23/34 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L24/14 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2023/4037 ,  H01L2023/4043 ,  H01L2023/405 ,  H01L2023/4062 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

Abstract: A fan-out wafer level package is provided. The fan-out wafer level package includes a semiconductor element, a molding compound, a first fan-out structure, a conductive heat spreader, and a plurality of solder balls. The semiconductor element includes a plurality of bonding pads. The molding compound covers the semiconductor element. The first fan-out structure is formed on the semiconductor element, wherein the first fan-out structure has a plurality of fan-out contacts electrically connected to the bonding pads. The conductive heat spreader is formed on the first fan-out structure, wherein the conductive heat spreader has a plurality of through holes filled with a conductive material. The solder balls are formed on the conductive heat spreader, wherein the solder balls are electrically connected to the first fan-out structure via the through holes filled with the conductive material.

Abstract translation: 提供扇形晶圆级封装。 扇形晶片级封装包括半导体元件，模塑料，第一扇出结构，导热散热器和多个焊球。 半导体元件包括多个接合焊盘。 模塑料覆盖半导体元件。 第一扇出结构形成在半导体元件上，其中第一扇出结构具有电连接到接合焊盘的多个扇出接点。 导电散热器形成在第一扇出结构上，其中导电散热器具有填充有导电材料的多个通孔。 焊球形成在导电散热器上，其中焊球通过填充有导电材料的通孔与第一扇出结构电连接。

公开(公告)号：US09269645B1

公开(公告)日：2016-02-23

申请号：US14521893

申请日：2014-10-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chu-Fu Lin ,  Chien-Li Kuo ,  Kuo-Ming Chen

IPC: H01L23/40 ,  H01L23/34 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L24/14 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2023/4037 ,  H01L2023/4043 ,  H01L2023/405 ,  H01L2023/4062 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

Abstract: A fan-out wafer level package is provided. The fan-out wafer level package includes a semiconductor element, a molding compound, a first fan-out structure, a conductive heat spreader, and a plurality of solder balls. The semiconductor element includes a plurality of bonding pads. The molding compound covers the semiconductor element. The first fan-out structure is formed on the semiconductor element, wherein the first fan-out structure has a plurality of fan-out contacts electrically connected to the bonding pads. The conductive heat spreader is formed on the first fan-out structure, wherein the conductive heat spreader has a plurality of through holes filled with a conductive material. The solder balls are formed on the conductive heat spreader, wherein the solder balls are electrically connected to the first fan-out structure via the through holes filled with the conductive material.

Abstract translation: 提供扇形晶圆级封装。 扇形晶片级封装包括半导体元件，模塑料，第一扇出结构，导热散热器和多个焊球。 半导体元件包括多个接合焊盘。 模塑料覆盖半导体元件。 第一扇出结构形成在半导体元件上，其中第一扇出结构具有电连接到接合焊盘的多个扇出接点。 导电散热器形成在第一扇出结构上，其中导电散热器具有填充有导电材料的多个通孔。 焊球形成在导电散热器上，其中焊球通过填充有导电材料的通孔与第一扇出结构电连接。

公开(公告)号：US20140203394A1

公开(公告)日：2014-07-24

申请号：US13747492

申请日：2013-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Tse Lin ,  Chu-Fu Lin ,  Chien-Li Kuo ,  Yung-Chang Lin

IPC: H01L23/538

CPC classification number: H01L21/76898 ,  H01L21/283 ,  H01L21/302 ,  H01L21/7685 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/16 ,  H01L28/60 ,  H01L2224/02317 ,  H01L2224/0401 ,  H01L2224/4824 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.

Abstract translation: 本发明提供一种用TSV电极形成芯片的方法。 提供具有第一表面和第二表面的基底。 从第二表面的一侧进行变薄处理，使得第二表面变成第三表面。 接下来，在衬底中形成穿过第一表面和第三表面的穿透。 图案化材料层形成在衬底上，其中图案化材料层具有开口以暴露穿透通孔。 导电层形成在第三表面上，从而同时在穿透孔中形成TSV电极和开口中的表面导电层。