公开(公告)号：US20150055125A1

公开(公告)日：2015-02-26

申请号：US13971776

申请日：2013-08-20

Applicant: United Microelectronics Corp.

Inventor： Wei-Jhe Tzai ,  Kuei-Chun Hung ,  Chun-Chi Yu ,  Chien-Hao Chen ,  Chia-Ching Lin

IPC: G03F9/00

CPC classification number: G03F7/70633

Abstract: A measurement method of an overlay mark is provided. An overlay mark on a wafer is measured with a plurality of different wavelength regions of an optical measurement tool, so as to obtain a plurality of overlay values corresponding to the wavelength regions. The overlay mark on the wafer is measured with an electrical measurement tool to obtain a reference overlay value. The wavelength region that corresponds to the overlay value closest to the reference overlay value is determined as a correct wavelength region for the overlay mark.

Abstract translation: 提供重叠标记的测量方法。 用光学测量工具的多个不同波长区域测量晶片上的覆盖标记，以便获得对应于波长区域的多个覆盖值。 用电测量工具测量晶片上的覆盖标记以获得参考覆盖值。 对应于最接近参考叠加值的覆盖值的波长区域被确定为覆盖标记的正确波长区域。

公开(公告)号：US20220392768A1

公开(公告)日：2022-12-08

申请号：US17341183

申请日：2021-06-07

Applicant: United Microelectronics Corp.

Inventor： Yi Jing Wang ,  Chia-Chang Hsu ,  Chien-Hao Chen ,  Chang-Mao Wang ,  Chun-Chi Yu

IPC: H01L21/033 ,  H01L21/311 ,  H01L23/544 ,  H01L21/66 ,  G03F7/20

Abstract: The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.

公开(公告)号：US09653404B1

公开(公告)日：2017-05-16

申请号：US15245161

申请日：2016-08-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Jing Wang ,  En-Chiuan Liou ,  Mei-Chen Chen ,  Han-Lin Zeng ,  Chia-Hung Lin ,  Chun-Chi Yu

IPC: H01L23/544

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446

Abstract: The present invention provides an overlay target. The overlay target includes a plurality of first pattern blocks and a plurality of second pattern blocks. The first pattern blocks and the second patterns blocks are arranged in array by being separated by at least one first gaps stretching along a first direction and at least one second gaps stretching along a second direction. Each first pattern block is composed of a plurality of first stripe patterns stretching along a third direction, and each second pattern block is composed of a plurality of second stripe patterns stretching along a fourth direction. The first direction is orthogonal to the second direction, the third direction and the fourth direction are 45 degrees relative to the first direction.

公开(公告)号：US09448471B2

公开(公告)日：2016-09-20

申请号：US14335949

申请日：2014-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Teng-Chin Kuo ,  Yuan-Chi Pai ,  Chun-Chi Yu

IPC: G03F1/38 ,  G03F7/20 ,  H01L21/027

CPC classification number: G03F1/38 ,  G03F7/20 ,  H01L21/0274

Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.

Abstract translation: 本发明提供一种用于在半导体衬底上制造结构的光掩模，其包括光掩模衬底，第一图案，第二图案和禁止图案。 第一有源区，第二有源区被限定在光掩模基板上，除了第一有源区和第二有源区之外的区域被定义为禁止区。 第一图案设置在第一有源区中并对应于半导体衬底上的第一结构。 第二图案设置在第二有源区域中，并且对应于半导体衬底上的第二结构。 禁止图案设置在禁止区域中，其中禁止图案具有超过光刻分辨能力的尺寸，并且不用于在半导体基板上形成任何相应的结构。 本发明还提供一种制造半导体结构的方法。

公开(公告)号：US20140120476A1

公开(公告)日：2014-05-01

申请号：US13661050

申请日：2012-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tuan-Yen Yu ,  Yuan-Chi Pai ,  Chun-Chi Yu

IPC: G03F7/20

CPC classification number: G03F7/2041 ,  G03F7/11 ,  G03F7/38 ,  G03F7/40

Abstract: A method of forming a photoresist pattern, in which, a substrate is coated with a photoresist layer, an exposure process is performed on the photoresist layer to expose the photoresist layer, the photoresist layer is rinsed with a surfactant after the exposure process is performed, and the photoresist layer is post-exposure baked after the photoresist layer is rinsed with the surfactant.

Abstract translation: 在光致抗蚀剂层上进行形成光致抗蚀剂图案的方法，其中基板涂覆有光致抗蚀剂层，曝光处理以曝光光致抗蚀剂层，在曝光处理之后用表面活性剂冲洗光致抗蚀剂层， 在用表面活性剂冲洗光致抗蚀剂层之后，对光致抗蚀剂层进行后曝光烘烤。

公开(公告)号：US12211699B2

公开(公告)日：2025-01-28

申请号：US17857158

申请日：2022-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yeh-Sheng Lin ,  Chang-Mao Wang ,  Chun-Chi Yu ,  Chung-Yi Chiu

IPC: H01L21/311 ,  H01L21/768

Abstract: A method of removing a step height on a gate structure includes providing a substrate. A gate structure is disposed on the substrate. A dielectric layer covers the gate structure and the substrate. Then, a composite material layer is formed to cover the dielectric layer. Later, part of the composite material layer is removed to form a step height disposed directly on the gate structure. Subsequently, a wet etching is performed to remove the step height. After the step height is removed, the dielectric layer is etched to form a first contact hole to expose the gate structure.

公开(公告)号：US20160018728A1

公开(公告)日：2016-01-21

申请号：US14335949

申请日：2014-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Teng-Chin Kuo ,  Yuan-Chi Pai ,  Chun-Chi Yu

IPC: G03F1/38 ,  H01L21/027 ,  G03F7/20

CPC classification number: G03F1/38 ,  G03F7/20 ,  H01L21/0274

Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.

Abstract translation: 本发明提供一种用于在半导体衬底上制造结构的光掩模，其包括光掩模衬底，第一图案，第二图案和禁止图案。 第一有源区，第二有源区被限定在光掩模基板上，除了第一有源区和第二有源区之外的区域被定义为禁止区。 第一图案设置在第一有源区中并对应于半导体衬底上的第一结构。 第二图案设置在第二有源区域中，并且对应于半导体衬底上的第二结构。 禁止图案设置在禁止区域中，其中禁止图案具有超过光刻分辨能力的尺寸，并且不用于在半导体基板上形成任何相应的结构。 本发明还提供一种制造半导体结构的方法。

公开(公告)号：US20150362905A1

公开(公告)日：2015-12-17

申请号：US14457136

申请日：2014-08-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chia-Chang Hsu ,  Teng-Chin Kuo ,  Chia-Hung Wang ,  Tuan-Yen Yu ,  Yuan-Chi Pai ,  Chun-Chi Yu

IPC: G05B19/18 ,  G03F7/20

CPC classification number: G03F7/70633 ,  G03F1/42 ,  G03F7/70491 ,  G05B19/188 ,  G05B2219/45027 ,  G05B2219/45031

Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.

Abstract translation: 校正重叠错误的方法包括以下步骤。 首先，捕获设置在基板上的覆盖标记，以生成重叠标记信息。 覆盖标记包括至少一对第一标记图案和至少第一标记图案上方的第二标记图案。 然后，计算叠加标记信息以产生两个第一标记图案之间的偏移值，并产生第二标记图案与第一标记图案之一之间的偏移值。 最后，偏移值用于补偿偏移值，以产生修正的移位值。

公开(公告)号：US09136140B2

公开(公告)日：2015-09-15

申请号：US14025524

申请日：2013-09-12

Applicant: United Microelectronics Corp.

Inventor： Wen-Liang Huang ,  Chia-Hung Lin ,  Chun-Chi Yu

IPC: H01L21/00 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/3088

Abstract: A patterning method is provided. First, a material layer is formed over a substrate. Thereafter, a plurality of directed self-assembly (DSA) patterns are formed on the material layer. Afterwards, a patterned photoresist layer is formed by using a single lithography process. The patterned photoresist layer covers a first portion of the DSA patterns and exposes a second portion of the DSA patterns. Further, the material layer is patterned by an etching process, using the patterned photoresist layer and the second portion of the DSA patterns as a mask.

Abstract translation: 提供了图案化方法。 首先，在基板上形成材料层。 此后，在材料层上形成多个定向自组装（DSA）图案。 之后，通过使用单个光刻工艺形成图案化的光致抗蚀剂层。 图案化的光致抗蚀剂层覆盖DSA图案的第一部分并且暴露DSA图案的第二部分。 此外，通过蚀刻工艺，使用图案化的光致抗蚀剂层和DSA图案的第二部分作为掩模来对材料层进行图案化。

公开(公告)号：US11043460B2

公开(公告)日：2021-06-22

申请号：US17000365

申请日：2020-08-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Wei Cheng ,  Bo-Jou Lu ,  Chun-Chi Yu

IPC: H01L23/544 ,  H01L21/66

Abstract: An overlay mark structure includes a plurality of first patterns of a previous layer and a plurality of second patterns of a current layer. Each of the second patterns includes a first section and a second section. The first section is disposed corresponding to one of the first patterns in a vertical direction. The first section partially overlaps the first pattern corresponding to the first section in the vertical direction. The second section is separated from the first section in an elongation direction of the second pattern. A part of the first pattern corresponding to the first section is disposed between the first section and the second section in the elongation direction of the second pattern. A measurement method of the overlay mark structure includes performing a diffraction-based overlay measurement between each of the first sections and the first pattern overlapping the first section.