公开(公告)号：US20180342602A1

公开(公告)日：2018-11-29

申请号：US15602114

申请日：2017-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： BIN TANG ,  Jubao Zhang ,  XIAOFEI HAN ,  CHAO JIANG ,  Hong Liao

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/788 ,  H01L27/11521

Abstract: A method of fabricating a floating gate includes providing a substrate divided into a cell region and a logic region. A silicon oxide layer and a silicon nitride layer cover the cell region and the logic region. Numerous STIs are formed in the silicon nitride layer, the silicon oxide layer, and the substrate. Later, the silicon nitride layer within the cell region is removed to form one recess between the adjacent STIs within the cell region while the silicon nitride layer within the logic region remains. Subsequently, a conductive layer is formed to fill the recess. The conductive layer is thinned to form a floating gate.

公开(公告)号：US09847351B2

公开(公告)日：2017-12-19

申请号：US15006123

申请日：2016-01-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lanxiang Wang ,  Hong Liao ,  Chao Jiang

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/77

CPC classification number: H01L27/1225 ,  H01L21/77 ,  H01L27/1218 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L2021/775

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a gate layer on the substrate; forming a first gate dielectric layer on the gate layer; forming a first channel layer on the first region and a second channel layer on the second region; and forming a first source/drain on the first channel layer and a second source/drain on the second channel layer.

公开(公告)号：US08890084B1

公开(公告)日：2014-11-18

申请号：US14016243

申请日：2013-09-03

Applicant: United Microelectronics Corp.

Inventor： Bin Guo ,  Xu Ma ,  Hong Liao

IPC: G01J1/42 ,  G01N23/00

CPC classification number: H01L22/30

Abstract: A method for analyzing circuit pattern is disclosed. The method includes the steps of: providing a plurality of monitor metal line structures formed on discrete locations of a substrate corresponding to different values of variable factors; performing a defect review to identify failure locations of the monitor metal line structures; determining a failure tendency of the monitor metal line structures so as to determine a boundary of the variable factors; and determining whether adjustment is to be made to product metal line structures.

Abstract translation: 公开了一种用于分析电路图案的方法。 该方法包括以下步骤：提供形成在对应于可变因子的不同值的衬底的离散位置上的多个监视金属线结构; 执行缺陷检查以识别监视器金属线结构的故障位置; 确定监视器金属线结构的故障趋势，以便确定可变因子的边界; 并且确定是否对产品金属线结构进行调整。

公开(公告)号：US10079204B2

公开(公告)日：2018-09-18

申请号：US15638352

申请日：2017-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao Su ,  Chow Yee Lim ,  Chao Jiang ,  Hong Liao

IPC: H01L23/48 ,  H01L23/522 ,  H01L27/11521 ,  H01L29/51 ,  H01L21/28 ,  H01L21/268 ,  H01L23/528 ,  G11C16/04

CPC classification number: H01L23/5226 ,  G11C16/0433 ,  G11C16/18 ,  G11C17/143 ,  G11C2216/26 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11546 ,  H01L29/518

Abstract: A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least two light-absorbing films above the floating gate, wherein each light-absorbing film is provided with at least one dummy via hole overlapping the floating gate, and a dielectric layer on each light-absorbing film and filling up the dummy via holes.

公开(公告)号：US09966465B1

公开(公告)日：2018-05-08

申请号：US15631529

申请日：2017-06-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hock-Chun Chin ,  Lan-Xiang Wang ,  Hong Liao ,  Chao Jiang ,  Chow-Yee Lim

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/423

CPC classification number: H01L29/78391 ,  H01L21/28282 ,  H01L21/28291 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/516 ,  H01L29/7883 ,  H01L29/792

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate, a first dielectric layer, a charge trapping layer, a ferroelectric material layer, and a gate layer. The first dielectric layer is disposed on the substrate, the charge trapping layer is disposed on the first dielectric layer, the ferroelectric material layer is disposed on the charge trapping layer, and the gate layer is disposed on the ferroelectric material layer.

公开(公告)号：US09728260B1

公开(公告)日：2017-08-08

申请号：US15140506

申请日：2016-04-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao Su ,  Chow Yee Lim ,  Chao Jiang ,  Hong Liao

IPC: H01L21/336 ,  G11C16/04 ,  H01L27/11521 ,  H01L29/51 ,  H01L21/28 ,  H01L21/268 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5226 ,  G11C16/0433 ,  H01L21/2686 ,  H01L21/28273 ,  H01L23/528 ,  H01L27/11521 ,  H01L29/518

Abstract: A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least one light-absorbing film above the floating gate, wherein at least one light-absorbing film is provided with dummy via holes overlapping the floating gate, and a dielectric layer on the light-absorbing film and filling up the dummy via holes.

公开(公告)号：US09607123B2

公开(公告)日：2017-03-28

申请号：US14598236

申请日：2015-01-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xing Hua Zhang ,  Chi-Fa Ku ,  Hong Liao ,  Ye Chao Li ,  Hui Yang

IPC: G06F17/50 ,  H01L23/58 ,  H01L21/66 ,  H01L23/528 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/10 ,  H01L27/06 ,  H01L23/00

CPC classification number: G06F17/5081 ,  H01L21/823871 ,  H01L22/34 ,  H01L23/10 ,  H01L23/528 ,  H01L23/562 ,  H01L23/58 ,  H01L27/0266 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor monitoring device includes a substrate, a die seal ring formed on the substrate, a deep n-typed well formed in the substrate under the die seal ring, and a monitoring device electrically connected to the die seal ring. The monitoring device is formed in a scribe line region defined on the substrate. A width of the deep n-typed well is larger than a width of the die seal ring.

公开(公告)号：US20160211187A1

公开(公告)日：2016-07-21

申请号：US14598236

申请日：2015-01-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xing Hua Zhang ,  Chi-Fa Ku ,  Hong Liao ,  Ye Chao Li ,  Hui Yang

IPC: H01L21/66 ,  H01L23/10 ,  H01L23/528 ,  G06F17/50

CPC classification number: G06F17/5081 ,  H01L21/823871 ,  H01L22/34 ,  H01L23/10 ,  H01L23/528 ,  H01L23/562 ,  H01L23/58 ,  H01L27/0266 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor monitoring device includes a substrate, a die seal ring formed on the substrate, a deep n-typed well formed in the substrate under the die seal ring, and a monitoring device electrically connected to the die seal ring. The monitoring device is formed in a scribe line region defined on the substrate. A width of the deep n-typed well is larger than a width of the die seal ring.

Abstract translation: 半导体监视装置包括基板，形成在基板上的模具密封环，形成在模具密封环下方的基板中的深n型阱，以及与模密封环电连接的监视装置。 监测装置形成在限定在基板上的划线区域中。 深n型井的宽度大于模具密封环的宽度。

公开(公告)号：US09209344B2

公开(公告)日：2015-12-08

申请号：US13647344

申请日：2012-10-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao Su ,  Hang Hu ,  Hong Liao

IPC: H01L21/00 ,  H01L31/18 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L31/1804 ,  H01L29/6659 ,  H01L29/7833 ,  Y02E10/547 ,  Y02P70/521

Abstract: The present invention provides a method of forming a doping region. A substrate is provided, and a poly-silicon layer is formed on the substrate. A silicon oxide layer is formed on the poly-silicon layer. An implant process is performed to form a doping region in the poly-silicon layer. The present invention further provides a method for forming a MOS.

Abstract translation: 本发明提供一种形成掺杂区域的方法。 提供基板，在基板上形成多晶硅层。 在多晶硅层上形成氧化硅层。 执行注入工艺以在多晶硅层中形成掺杂区域。 本发明还提供一种用于形成MOS的方法。