公开(公告)号：US20220270942A1

公开(公告)日：2022-08-25

申请号：US17680308

申请日：2022-02-25

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nataporn Charusabha ,  Kunakorn Kaoson ,  Saravuth Sirinorakul ,  Sukhontip Jaikongkaew ,  Il Kwon Shim

IPC: H01L23/24 ,  H01L23/00 ,  H01L23/367 ,  H01L21/56

Abstract: A flip chip package is disclosed. The package includes a leadframe surrounding a flip chip. The leadframe and flip chip are encapsulated by a mold compound. The leadframe provides package support to enhance the mechanical stability of the package. In some cases, a heat dissipating structure is disposed on top of the package, connecting the flip chip to enhance heat dissipation.

公开(公告)号：US12302657B2

公开(公告)日：2025-05-13

申请号：US17664510

申请日：2022-05-23

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Emmanuel Espiritu ,  Il Kwon Shim ,  Jeffrey Punzalan ,  Teddy Joaquin Carreon

IPC: H01L27/146 ,  H01L23/31 ,  H10F39/00

Abstract: A semiconductor device has a substrate. A semiconductor die including a photosensitive circuit is disposed over the substrate. A shield is disposed over the substrate and semiconductor die with a first opening of the shield disposed over the photosensitive circuit. An outer section of the shield is attached to the substrate and includes a second opening. An encapsulant is deposited over the substrate and semiconductor die. The encapsulant extends into the first opening and a first area between the shield and substrate while a second area over the photosensitive circuit remains devoid of the encapsulant.

公开(公告)号：US12211863B2

公开(公告)日：2025-01-28

申请号：US17394365

申请日：2021-08-04

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Il Kwon Shim ,  Jeffrey Punzalan ,  Emmanuel Espiritu ,  Allan Ilagan ,  Teddy Joaquin Carreon

IPC: H01L27/14 ,  H01L23/00 ,  H01L27/146

Abstract: A semiconductor package is disclosed. The package includes a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die region. A die having first and second major die surfaces is attached onto the die region. The second major die surface is attached to the die region. The first major die surface includes a sensor region and a cover adhesive region surrounding the sensor region. The package also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the sensor region. The protective cover includes a recessed structure on the second major cover surface. The recessed structure is located above die bond pads on the die to create an elevated space over peak portions of wire bonds on the die bond pads. An encapsulant is disposed on the package substrate to cover exposed portions of the package substrate, die and bond wires and side surfaces of the protective cover, while leaving the first major cover surface exposed.

公开(公告)号：US20240186346A1

公开(公告)日：2024-06-06

申请号：US18516997

申请日：2023-11-22

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Jeffrey Punzalan ,  Catherine Cheh Yee Chang ,  Il Kwon Shim

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14618 ,  H01L24/45 ,  H01L24/48 ,  H01L27/14683 ,  H01L24/32 ,  H01L27/14636 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48227

Abstract: A semiconductor package for a sensor is disclosed. The package includes an opaque layer on the encapsulation to prevent the wire bonds encased by the encapsulation from being visible to the naked eye. This reduces or prevents reflectance which improves the performance of the sensor. In some cases, the opaque layer extends beyond the encapsulation to cover a peripheral portion of the cover to form a cover opaque region. The cover opaque region reduces or prevents flaring and scattering of light, further enhancing the performance of the sensor.

公开(公告)号：US20230343668A1

公开(公告)日：2023-10-26

申请号：US18302627

申请日：2023-04-18

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Il Kwon Shim ,  Ronnie M. De Villa ,  Dzafir Bin Mohd Shariff

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/3171 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L21/4846 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/20 ,  H01L24/19 ,  H01L23/3185 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2224/02381 ,  H01L2224/05083 ,  H01L2224/05111 ,  H01L2224/05008 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/05611 ,  H01L2224/05655 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L2224/05571 ,  H01L2224/0401 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/245 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/24011 ,  H01L2224/05082 ,  H01L2224/05027 ,  H01L2224/05024 ,  H01L2224/05018 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/13124 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13116 ,  H01L2224/13113 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L23/49866 ,  H01L2224/19 ,  H01L2224/215 ,  H01L2224/2101

Abstract: A semiconductor device has a substrate and a first insulating layer formed over a first major surface of the substrate. A first redistribution layer is formed over the first insulating layer. A second insulating layer is formed over the first redistribution layer. A second redistribution layer can be formed over the second insulating layer, and a third insulating layer can be formed over the second redistribution layer. A protection layer is formed over a second major surface of the substrate for warpage control. A conductive layer is formed over the first redistribution layer, and a bump is formed over the conductive layer. An under bump metallization can be formed under the bump. The protection layer extends over a side surface of the substrate between the first major surface and second major surface. The protection layer further extends over a side surface of the first insulating layer.