公开(公告)号：US11901308B2

公开(公告)日：2024-02-13

申请号：US17382283

申请日：2021-07-21

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Saravuth Sirinorakul ,  Il Kwon Shim ,  Kok Chuen Lock ,  Roel Adeva Robles ,  Eakkasit Dumsong

IPC: H01L23/552 ,  H01L23/36 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/495

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49503 ,  H01L24/32 ,  H01L2224/32245

Abstract: The present disclosure is directed to improving EMI shielding to provide more reliable semiconductor packages. The semiconductor package may be, for example, a lead frame including one or multiple dies attached thereto. The semiconductor package may include only wire bonds or a combination of clip bonds and wire bonds. An integrated shielding structure may be disposed in between the package substrate and the encapsulant to shield internal and/or external EMI. For example, a top surface of the integrated shield structure is exposed.

公开(公告)号：US11227818B2

公开(公告)日：2022-01-18

申请号：US16942715

申请日：2020-07-29

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Wing Keung Lam ,  Saravuth Sirinorakul ,  Kok Chuen Lock ,  Roel Adeva Robles

IPC: H01L23/495 ,  H01L23/48 ,  H01L21/00 ,  H01R9/00 ,  H05K7/00 ,  H05K7/18 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L25/16 ,  H01L23/00 ,  H01L23/498

Abstract: An embodiment related to a stacked package is disclosed. The stacked package includes a conductive gang with gang legs electrically coupling a second component stacked over a first die to a package substrate. The first die is mounted over a die attach region of the package substrate and electrically coupled to the package substrate.

公开(公告)号：US10658277B2

公开(公告)日：2020-05-19

申请号：US16057792

申请日：2018-08-07

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Antonio Bambalan Dimaano, Jr. ,  Nataporn Charusabha ,  Saravuth Sirinorakul ,  Preecha Joymak ,  Roel Adeva Robles

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L23/433

Abstract: Embodiments of the present invention are directed to a semiconductor package with improved thermal performance. The semiconductor package includes a package substrate comprising a top substrate surface and a bottom substrate surface. The package substrate comprises a thickness extending from the top substrate surface to the bottom substrate surface. A heat spreader is disposed on the top substrate surface. The heat spreader comprises a thickness extending from a top planar surface to a bottom planar surface of the heat spreader. The top planar surface of the heat spreader is defined with a die region and a non-die region surrounding the die region. A semiconductor die is directly disposed on the top planar surface of the heat spreader in the die region. The thickness of the heat spreader is greater relative to the thickness of the package substrate.

公开(公告)号：US10204850B1

公开(公告)日：2019-02-12

申请号：US15624586

申请日：2017-06-15

Applicant: UTAC Headquarters PTE, LTD.

Inventor： Somchai Nondhasitthichai ,  Saravuth Sirinorakul ,  Woraya Benjavasukul

IPC: H01L23/495 ,  H01L23/31

Abstract: Embodiments of the present invention are directed to a semiconductor package with partial plating on contact surfaces. The semiconductor package includes a top surface, a bottom surface that is opposite the top surface, and side surfaces between the top surface and the bottom surface. Each of the side surfaces includes a step such that the area of the bottom surface is smaller than the area of the top surface. The semiconductor package includes a plurality of contacts that is located at peripheral edges of the bottom surface. Each of the plurality of contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a curved surface located at a corresponding step. In some embodiments, the first surface and the curved surface are plated, while the second surface is exposed (not plated).

公开(公告)号：US10163658B2

公开(公告)日：2018-12-25

申请号：US15667433

申请日：2017-08-02

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L21/48 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to activate areas of each molding compound layer of the semiconductor package. Each compound filler in the molding compound layer has a metal interior and an insulating outermost shell. The activated molding compound areas in the molding compound layer become metallized in an electroless plating solution to build conductive paths on the molding compound surface, while properties of non-activated molding compound areas are not changed.

公开(公告)号：US09805955B1

公开(公告)日：2017-10-31

申请号：US15347641

申请日：2016-11-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L21/4828 ,  H01L21/481 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49527 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49558 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49805 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2224/45664 ,  H01L2224/45644

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.

公开(公告)号：US09773722B1

公开(公告)日：2017-09-26

申请号：US14706864

申请日：2015-05-07

Applicant: UTAC Headquarters PTE, LTD.

Inventor： Somchai Nondhasitthichai ,  Saravuth Sirinorakul ,  Woraya Benjavasukul

IPC: H01L23/495 ,  H01L23/31

CPC classification number: H01L23/49582 ,  H01L21/4828 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/014

Abstract: Embodiments of the present invention are directed to a semiconductor package with partial plating on contact surfaces. The semiconductor package includes a top surface, a bottom surface that is opposite the top surface, and side surfaces between the top surface and the bottom surface. Each of the side surfaces includes a step such that the area of the bottom surface is smaller than the area of the top surface. The semiconductor package includes a plurality of contacts that is located at peripheral edges of the bottom surface. Each of the plurality of contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a curved surface located at a corresponding step. In some embodiments, the first surface and the curved surface are plated, while the second surface is exposed (not plated).

公开(公告)号：US10707161B2

公开(公告)日：2020-07-07

申请号：US16056541

申请日：2018-08-07

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Hua Hong Tan ,  Wilson Poh Leng Ong ,  Kriangsak Sae Le ,  Saravuth Sirinorakul ,  Somsak Phukronghin ,  Paweena Phatto

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/055 ,  H01L23/16 ,  H01L23/31 ,  H01L21/52 ,  H01L21/56 ,  H01L23/04 ,  H01L23/24 ,  H01L23/00

Abstract: An improved method for forming a semiconductor package is disclosed herein. The method includes forming a multi-layer package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate comprises a recess region. A semiconductor die is attached to the die region within the recess region. A dam structure is formed within the recess region. The dam structure surrounds the semiconductor die and extends upward to a height below the first major surface of the package substrate. A liquid encapsulant material is dispensed into the recess region. The liquid encapsulant material is surrounded by the dam structure. The liquid encapsulant extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.

公开(公告)号：US10276477B1

公开(公告)日：2019-04-30

申请号：US15590878

申请日：2017-05-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Keith M. Edwards ,  Suebphong Yenrudee ,  Albert Loh

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/78

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple leadframe routing layers in a plated and etched copper terminal semiconductor package by removing unwanted areas of each leadframe to create conductive paths on an associated leadframe layer of the semiconductor package.

公开(公告)号：US10269686B1

公开(公告)日：2019-04-23

申请号：US15167724

申请日：2016-05-27

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Suebphong Yenrudee ,  Saravuth Sirinorakul

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/311 ,  H01L21/48 ,  H01L21/683

Abstract: Embodiments of the present invention relate to a semiconductor package that includes a locking feature. The locking feature is provided by an unnatural surface roughness of a first molding compound to increase adhesion with a second molding compound. Surfaces of first molding compound are roughened by an abrasion process such that the surfaces are rougher than a natural surface roughness. The roughened surfaces of the first molding compound provide better adhesion of the second molding compound to the roughened surfaces than to untreated surfaces (e.g., surfaces with the natural surface roughness).