公开(公告)号：US09627036B2

公开(公告)日：2017-04-18

申请号：US14822911

申请日：2015-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Yu-Cheng Tung ,  Chin-Sheng Yang

IPC: H01L21/28 ,  H01L23/535 ,  H01L27/11 ,  H01L29/66 ,  G11C11/412 ,  H01L27/02

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104

Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.

公开(公告)号：US20160276434A1

公开(公告)日：2016-09-22

申请号：US15166271

申请日：2016-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun Jen Chen ,  Bin-Siang Tsai ,  Tsai-Yu Wen ,  Yu Shu Lin ,  Chin-Sheng Yang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/41

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02587 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/76224 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/16 ,  H01L29/165 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires.

Abstract translation: 提供半导体器件。 半导体器件包括衬底; 设置在衬底上的第一纳米线; 设置在衬底上的第二纳米线; 形成在第一和第二纳米线的第一端处的第一焊盘，形成在第一和第二纳米线的第二端处的第二焊盘，其中焊盘包括与纳米线不同的材料; 以及围绕第一和第二纳米线的每一个的至少一部分的栅极。

公开(公告)号：US09331184B2

公开(公告)日：2016-05-03

申请号：US13914641

申请日：2013-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Sheng Yang ,  Chien-Hung Chen

IPC: H01L29/66 ,  H01L29/792 ,  H01L21/28

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) device is disclosed. The SONOS device includes a substrate; a first oxide layer on the substrate; a silicon-rich trapping layer on the first oxide layer; a nitrogen-containing layer on the silicon-rich trapping layer; a silicon-rich oxide layer on the nitrogen-containing layer; and a polysilicon layer on the silicon-rich oxide layer.

Abstract translation: 公开了一种氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）器件。 SONOS器件包括衬底; 衬底上的第一氧化物层; 在所述第一氧化物层上的富硅捕获层; 富硅捕获层上的含氮层; 含氮层上的富硅氧化物层; 和富硅氧化物层上的多晶硅层。

公开(公告)号：US10262982B2

公开(公告)日：2019-04-16

申请号：US15785447

申请日：2017-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hsien Hsu ,  Chien-Fu Chen ,  Cheng-Yang Tsai ,  Wei-Jen Wang ,  Chao-Wei Lin ,  Zhi-Hong Huang ,  Cheng-Tsung Ku ,  Chin-Sheng Yang

IPC: H01L27/02 ,  H03K19/0948 ,  H01L23/528 ,  H01L23/522 ,  H01L27/092 ,  H01L29/167 ,  H03K19/20

Abstract: The present invention provides an integrated circuit with a standard cell of an inverter. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

公开(公告)号：US20170178716A1

公开(公告)日：2017-06-22

申请号：US15448599

申请日：2017-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Yu-Cheng Tung ,  Chin-Sheng Yang

IPC: G11C11/417 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104

Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.

公开(公告)号：US20150236150A1

公开(公告)日：2015-08-20

申请号：US14183541

申请日：2014-02-19

Applicant: United Microelectronics Corp.

Inventor： Ming-Shing Chen ,  Ming-Hui Chang ,  Wei-Ting Wu ,  Ying-Chou Lai ,  Horng-Nan Chern ,  Chorng-Lih Young ,  Chin-Sheng Yang

IPC: H01L29/78 ,  H01L29/45 ,  H03K3/012 ,  H01L29/10 ,  H01L29/49 ,  H01L29/788 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L21/761 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7835

Abstract: Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided.

Abstract translation: 提供一种半导体器件，包括P型衬底，P型第一阱区，N型第二阱区，栅极，N型源极和漏极区，虚拟栅极和N型阱阱区域 。 第一阱区位于衬底中。 第二阱区位于靠近第一阱区的衬底中。 栅极位于基板上并且覆盖第一阱区域的一部分和第二阱区域的一部分。 源极区位于栅极一侧的第一阱区中。 漏极区域位于栅极另一侧的第二阱区域中。 虚拟栅极位于栅极和漏极区域之间的衬底上。 深井区域位于基板中并围绕第一和第二井区域。 还提供了一种半导体器件的操作方法。

公开(公告)号：US10090289B1

公开(公告)日：2018-10-02

申请号：US15813163

申请日：2017-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hsien Hsu ,  Chien-Fu Chen ,  Cheng-Yang Tsai ,  Wei-Jen Wang ,  Chao-Wei Lin ,  Zhi-Hong Huang ,  Cheng-Tsung Ku ,  Chin-Sheng Yang

IPC: H01L27/02 ,  H01L23/522 ,  H01L27/088 ,  H01L23/528

Abstract: The present invention provides an integrated circuit with a dummy standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Plural sets of short contact plug and long contact plug disposed between the first dummy gate, the second dummy gate and the gate structures; a doping region overlaps with the long contact plugs; a gate contact plug disposed on the gate structures; plural contact plugs disposed on and electrical contact the long contact plugs; A metal layer includes the first metal line, the second metal line.

公开(公告)号：US09653549B2

公开(公告)日：2017-05-16

申请号：US15166271

申请日：2016-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun Jen Chen ,  Bin-Siang Tsai ,  Tsai-Yu Wen ,  Yu Shu Lin ,  Chin-Sheng Yang

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L29/78 ,  H01L29/165 ,  H01L29/775 ,  H01L29/41

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02587 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/76224 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/16 ,  H01L29/165 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires.

公开(公告)号：US20160329400A1

公开(公告)日：2016-11-10

申请号：US15215609

申请日：2016-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Chin-Sheng Yang ,  Chun-Jen Chen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02603 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/31658 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.

Abstract translation: 形成纳米线的方法包括提供基底。 蚀刻衬底以形成至少一个鳍。 随后，在鳍的上部形成第一外延层。 之后，在翅片的中间部分形成底切。 形成第二外延层以填充底切。 最后，将鳍状物，第一外延层和第二外延层氧化以将第一外延层和第二外延层冷凝成含锗纳米线。

公开(公告)号：US20160315100A1

公开(公告)日：2016-10-27

申请号：US14714352

申请日：2015-05-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Sheng Yang

IPC: H01L27/12 ,  H01L29/24 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1225 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7842

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first transistor and a second transistor. The first transistor is disposed on a substrate and comprises a gate electrode, a gate dielectric layer and a first source/drain. The second transistor includes the gate electrode and a channel layer disposed on the gate electrode.

Abstract translation: 半导体器件及其形成方法，所述半导体器件包括第一晶体管和第二晶体管。 第一晶体管设置在衬底上，并且包括栅极电极，栅极电介质层和第一源极/漏极。 第二晶体管包括栅电极和设置在栅电极上的沟道层。