公开(公告)号：US10692875B2

公开(公告)日：2020-06-23

申请号：US16177812

申请日：2018-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wang Xiang ,  Chia-Ching Hsu ,  Chun-Sung Huang ,  Yung-Lin Tseng ,  Wei-Chang Liu ,  Shen-De Wang

IPC: H01L27/115 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/1157

Abstract: A memory structure including a substrate, at least one stacked gate structure, a first spacer conductive layer, and a first contact is provided. The stacked gate structure is located on the substrate and includes a control gate. The control gate extends in a first direction. The first spacer conductive layer is located on one sidewall of the control gate and is electrically insulated from the control gate. The first spacer conductive layer includes a first merged spacer portion and a first non-merged spacer portion. A line width of the first merged spacer portion is greater than a line width of the first non-merged spacer portion. The first contact is connected to the first merged spacer portion. The memory structure can have a larger process window of contact.

公开(公告)号：US09748256B2

公开(公告)日：2017-08-29

申请号：US14924525

申请日：2015-10-27

Applicant: United Microelectronics Corp.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wang Xiang ,  Yi-Shan Chiu ,  Wei Ta

IPC: H01L29/788 ,  H01L27/11524 ,  H01L21/28

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: Provided is a semiconductor device including a memory gate structure and a select gate structure. The memory gate structure is closely adjacent to the select gate structure. Besides, an air gap encapsulated by an insulating layer is disposed between the memory gate structure and the select gate structure.

公开(公告)号：US20170077110A1

公开(公告)日：2017-03-16

申请号：US14924525

申请日：2015-10-27

Applicant: United Microelectronics Corp.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wang Xiang ,  Yi-Shan Chiu ,  Wei Ta

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: Provided is a semiconductor device including a memory gate structure and a select gate structure. The memory gate structure is closely adjacent to the select gate structure. Besides, an air gap encapsulated by an insulating layer is disposed between the memory gate structure and the select gate structure.

Abstract translation: 提供了包括存储器栅极结构和选择栅极结构的半导体器件。 存储器栅极结构与选择栅极结构紧密相邻。 此外，由绝缘层封装的气隙设置在存储器栅极结构和选择栅极结构之间。

公开(公告)号：US09455322B1

公开(公告)日：2016-09-27

申请号：US14862118

申请日：2015-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Shan Chiu ,  Shen-De Wang ,  Weichang Liu ,  Wei Ta ,  Zhen Chen ,  Wang Xiang

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/788 ,  H01L27/115 ,  H01L29/51

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7881

Abstract: A flash cell forming process includes the following steps. A first gate is formed on a substrate. A first spacer is formed at a side of the first gate, where the first spacer includes a bottom part and a top part. The bottom part is removed, thereby an undercut being formed. A first selective gate is formed beside the first spacer and fills into the undercut. The present invention also provides a flash cell formed by said flash cell forming process. The flash cell includes a first gate, a first spacer and a first selective gate. The first gate is disposed on a substrate. The first spacer is disposed at a side of the first gate, where the first spacer has an undercut at a bottom part, and therefore exposes the substrate. The first selective gate is disposed beside the first spacer and extends into the undercut.

Abstract translation: 闪光单元形成工艺包括以下步骤。 在基板上形成第一栅极。 第一间隔件形成在第一栅极的一侧，其中第一间隔件包括底部和顶部。 底部被去除，从而形成底切。 在第一间隔物旁边形成第一选择栅，并填入底切。 本发明还提供了一种由所述闪存单元形成工艺形成的闪光单元。 闪存单元包括第一栅极，第一间隔物和第一选择栅极。 第一栅极设置在基板上。 第一间隔件设置在第一栅极的一侧，其中第一间隔件在底部具有底切，因此露出基板。 第一选择栅设置在第一间隔物旁边并延伸到底切中。

公开(公告)号：US11444095B2

公开(公告)日：2022-09-13

申请号：US17229848

申请日：2021-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wang Xiang ,  Chia-Ching Hsu ,  Shen-De Wang ,  Weichang Liu

IPC: H01L29/76 ,  H01L29/66 ,  H01L27/092 ,  H01L27/11568 ,  H01L27/11573 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/311

Abstract: A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.

公开(公告)号：US20210119004A1

公开(公告)日：2021-04-22

申请号：US17134131

申请日：2020-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Sung Huang ,  Shen-De Wang ,  Chia-Ching Hsu ,  Wang Xiang

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/792

Abstract: A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.

公开(公告)号：US10903326B2

公开(公告)日：2021-01-26

申请号：US16246538

申请日：2019-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Sung Huang ,  Shen-De Wang ,  Chia-Ching Hsu ,  Wang Xiang

IPC: H01L29/423 ,  H01L29/792 ,  H01L29/40

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; forming a second gate structure on the substrate and on one side of the first gate structure; forming a third gate structure on the substrate and on another side of the first gate structure; forming source/drain regions adjacent to the second gate structure and the third gate structure; and forming contact plugs to contact the first gate structure, the second gate structure, the third gate structure, and the source/drain regions.

公开(公告)号：US20200227531A1

公开(公告)日：2020-07-16

申请号：US16246538

申请日：2019-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Sung Huang ,  Shen-De Wang ,  Chia-Ching Hsu ,  Wang Xiang

IPC: H01L29/423 ,  H01L29/792 ,  H01L29/40

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; forming a second gate structure on the substrate and on one side of the first gate structure; forming a third gate structure on the substrate and on another side of the first gate structure; forming source/drain regions adjacent to the second gate structure and the third gate structure; and forming contact plugs to contact the first gate structure, the second gate structure, the third gate structure, and the source/drain regions.

公开(公告)号：US10699958B2

公开(公告)日：2020-06-30

申请号：US16116730

申请日：2018-08-29

Applicant: United Microelectronics Corp.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wang Xiang ,  Wei Ta ,  Ling-Gang Fang ,  Shang Xue

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8239

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first gate, a gate dielectric layer, a pair of second gates, a first spacer, and a second spacer. The first gate is disposed on a substrate. The gate dielectric layer is disposed between the first gate and the substrate. The pair of second gates are disposed on the substrate and respectively located at two sides of the first gate, wherein top surfaces of the pair of second gates are higher than a top surface of the first gate. The first spacer is disposed on sidewalls of the pair of second gates protruding from the top surface of the first gate and covers the top surface of the first gate. The second spacer is disposed between the gate dielectric layer and the pair of second gates, between the first gate and the pair of second gates, and between the first spacer and the pair of second gates.

公开(公告)号：US10062705B1

公开(公告)日：2018-08-28

申请号：US15487404

申请日：2017-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Xu ,  JiZhou Han ,  Wang Xiang

IPC: H01L27/11568 ,  H01L27/11573 ,  H01L21/02 ,  H01L29/51 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L21/02164 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A method of manufacturing a flash memory includes providing a substrate, a memory gate on the substrate, a hard mask on the memory gate, a spacer on a sidewall of the memory gate, and a select gate disposed on a sidewall of the spacer. A first silicon oxide layer is formed to conformally cover the memory gate, the hard mask, the spacer, and the select gate. A thickness of the first silicon oxide layer is smaller than 0.54 of a thickness of the hard mask. Later, the first silicon oxide layer is thinned by a dry etching process. After that, the first silicon oxide layer and the hard mask are entirely removed by a wet etching process.