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公开(公告)号：US20070228569A1
公开(公告)日：2007-10-04
申请号：US11783186
申请日：2007-04-06
CPC分类号： H01L21/76849 , H01L21/76819 , H01L21/7685 , Y10S438/976 , Y10T29/41
摘要： The present invention provides an interconnects-forming method and an interconnects-forming apparatus which can minimize the lowering of processing accuracy in etching, minimize light exposure processing for the formation of interconnect recesses in the production of multi-level interconnects, improve the electromigration resistance of interconnects without impairing the electrical properties of the interconnects, and enhance the reliability of the device. The interconnects-forming method, includes providing interconnect recesses in an insulating film formed in a surface of a substrate; embedding an interconnect material in the interconnect recesses while forming a metal film of the interconnect material on a surface of the insulating film; removing an extra metal material other than the metal material in the interconnect recesses and flattening the substrate surface, thereby forming interconnects; forming a first protective film of a conductive material selectively on exposed surfaces of the interconnects; forming a second protective film on the surface of the substrate having the thus-formed first protective film; forming an interlevel insulating film on the surface of the substrate having the thus-formed second protective film; and flattening a surface of the interlevel insulating film.
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公开(公告)号：US07217653B2
公开(公告)日：2007-05-15
申请号：US10896014
申请日：2004-07-22
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76819 , H01L21/7685 , Y10S438/976 , Y10T29/41
摘要： The present invention provides an interconnects-forming method and an interconnects-forming apparatus which can minimize the lowering of processing accuracy in etching, minimize light exposure processing for the formation of interconnect recesses in the production of multi-level interconnects, improve the electromigration resistance of interconnects without impairing the electrical properties of the interconnects, and enhance the reliability of the device. The interconnects-forming method, includes providing interconnect recesses in an insulating film formed in a surface of a substrate; embedding an interconnect material in the interconnect recesses while forming a metal film of the interconnect material on a surface of the insulating film; removing an extra metal material other than the metal material in the interconnect recesses and flattening the substrate surface, thereby forming interconnects; forming a first protective film of a conductive material selectively on exposed surfaces of the interconnects; forming a second protective film on the surface of the substrate having the thus-formed first protective film; forming an interlevel insulating film on the surface of the substrate having the thus-formed second protective film; and flattening a surface of the interlevel insulating film.
摘要翻译： 本发明提供一种互连形成方法和互连形成装置，其能够最小化蚀刻中的处理精度的降低，使在多层互连的制造中形成互连凹槽的光曝光处理最小化，提高电镀迁移电阻 互连，而不损害互连的电性能，并且增强器件的可靠性。 互连形成方法包括在形成在基板的表面中的绝缘膜中提供互连凹槽; 在互连凹槽中嵌入互连材料，同时在绝缘膜的表面上形成互连材料的金属膜; 除去互连凹部中的金属材料以外的多余的金属材料，使基板表面变平，从而形成互连件; 在互连的暴露表面上选择性地形成导电材料的第一保护膜; 在具有如此形成的第一保护膜的基板的表面上形成第二保护膜; 在具有如此形成的第二保护膜的基板的表面上形成层间绝缘膜; 并平坦化层间绝缘膜的表面。
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公开(公告)号：US20050064702A1
公开(公告)日：2005-03-24
申请号：US10896014
申请日：2004-07-22
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76819 , H01L21/7685 , Y10S438/976 , Y10T29/41
摘要： The present invention provides an interconnects-forming method and an interconnects-forming apparatus which can minimize the lowering of processing accuracy in etching, light exposure or the like processing for the formation of interconnect recesses in the production of multi-level interconnects, can improve the electromigration resistance of interconnects without impairing the electrical properties of the interconnects, and can enhance the reliabilityof the device. The interconnects-formingmethod, including: providing interconnect recesses in an insulating film formed in a surface of a substrate; embedding an interconnect material in the interconnect recesses while forming a metal film of the interconnect material on a surface of the insulating film; removing an extra metal material other than the metal material in the interconnect recesses and flattening the substrate surface, thereby forming interconnects; forming a first protective film of a conductive material selectively on exposed surfaces of the interconnects; forming a second protective film on the surface of the substrate having the thus-formed first protective film; forming an interlevel insulating film on the surface of the substrate having the thus-formed second protective film; and flattening a surface of the interlevel insulating film.
摘要翻译： 本发明提供一种互连形成方法和互连形成装置，其可以最小化在制造多层互连中形成互连凹槽的蚀刻，曝光等处理中的处理精度的降低， 互连的电迁移电阻，而不损害互连的电性能，并且可以提高器件的可靠性。 所述互连形成方法包括：在形成在基板的表面中的绝缘膜中提供互连凹槽; 在互连凹槽中嵌入互连材料，同时在绝缘膜的表面上形成互连材料的金属膜; 除去互连凹部中的金属材料以外的多余的金属材料，使基板表面变平，从而形成互连件; 在互连的暴露表面上选择性地形成导电材料的第一保护膜; 在具有如此形成的第一保护膜的基板的表面上形成第二保护膜; 在具有如此形成的第二保护膜的基板的表面上形成层间绝缘膜; 并平坦化层间绝缘膜的表面。
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公开(公告)号：US07407821B2
公开(公告)日：2008-08-05
申请号：US10874245
申请日：2004-06-24
申请人： Xinming Wang , Daisuke Takagi , Akihiko Tashiro , Akira Fukunaga
发明人： Xinming Wang , Daisuke Takagi , Akihiko Tashiro , Akira Fukunaga
IPC分类号： H01L21/66
CPC分类号： H01L21/76849 , C23C18/1608 , C23C18/1675 , C23C18/1692 , C23C18/1879 , H01L21/288 , H01L21/76864 , H01L21/76874 , H01L22/12 , H01L22/20 , H01L2223/54466
摘要： There is provided a substrate processing method and apparatus which can measure and monitor thickness and/or properties of a film formed on a substrate as needed, and quickly correct a deviation in process conditions, and which can therefore stably provide a product of constant quality. A substrate processing method for processing a substrate having a metal and an insulating material exposed on its surface in such a manner that a film thickness of the metal, with an exposed surface of the metal as a reference plane, is selectively or preferentially changed, including measuring a change in the film thickness and/or a film property of the metal during and/or immediately after processing, and monitoring processing and adjusting processing conditions based on results of this measurement.
摘要翻译： 提供了可以根据需要测量和监测在基板上形成的膜的厚度和/或性能的基板处理方法和装置，并且可以快速地校正工艺条件的偏差，因此可以稳定地提供恒定品质的产品。 一种基板处理方法，用于处理具有金属和绝缘材料的基板，所述基板以其金属的暴露表面作为基准面的方式选择性地或优先地改变的金属的膜厚度包括 测量处理期间和/或紧随其后的金属的膜厚度和/或膜性质的变化，以及基于该测量结果的监测处理和调整处理条件。
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公开(公告)号：US20050009213A1
公开(公告)日：2005-01-13
申请号：US10874245
申请日：2004-06-24
申请人： Xinming Wang , Daisuke Takagi , Akihiko Tashiro , Akira Fukunaga
发明人： Xinming Wang , Daisuke Takagi , Akihiko Tashiro , Akira Fukunaga
IPC分类号： G01B21/08 , C23C18/16 , C23C18/31 , C23F1/08 , H01L21/288 , H01L21/3205 , H01L21/66 , H01L21/768 , H01L21/00
CPC分类号： H01L21/76849 , C23C18/1608 , C23C18/1675 , C23C18/1692 , C23C18/1879 , H01L21/288 , H01L21/76864 , H01L21/76874 , H01L22/12 , H01L22/20 , H01L2223/54466
摘要： There is provided a substrate processing method and apparatus which can measure and monitor the thickness and/or properties of a film formed on a substrate as needed, and quickly correct a deviation in the process conditions, and which can therefore stably provide a product of constant quality. A substrate processing method for processing a substrate with a metal and an insulating material exposed on its surface in such a manner that the film thickness of the metal portion with the exposed surface of the metal as a reference plane is selectively or preferentially changed, including measuring a change in the film thickness and/or a film property of the metal portion during and/or immediately after processing, and monitoring the processing and adjusting the processing conditions based on the results of measurement.
摘要翻译： 提供了可以根据需要测量和监测在基板上形成的膜的厚度和/或性能的基板处理方法和装置，并且可以快速校正工艺条件的偏差，因此可以稳定地提供恒定的产品 质量。 一种基板处理方法，用于以金属的暴露表面作为基准面的金属部分的膜厚选择性地或优先地改变的方式处理具有金属和绝缘材料的基板，该金属和绝缘材料暴露在其表面上，包括测量 在处理期间和/或紧随其后的金属部分的膜厚度和/或膜特性的变化，并且基于测量结果监视处理和调整处理条件。
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公开(公告)号：US20090000549A1
公开(公告)日：2009-01-01
申请号：US12216147
申请日：2008-06-30
申请人： Xinming Wang , Daisuke Takagi , Akihiko Tashiro , Akira Fukunaga
发明人： Xinming Wang , Daisuke Takagi , Akihiko Tashiro , Akira Fukunaga
IPC分类号： B05C11/00
CPC分类号： H01L21/76849 , C23C18/1608 , C23C18/1675 , C23C18/1692 , C23C18/1879 , H01L21/288 , H01L21/76864 , H01L21/76874 , H01L22/12 , H01L22/20 , H01L2223/54466
摘要： There is provided a substrate processing method and apparatus which can measure and monitor thickness and/or properties of a film formed on a substrate as needed, and quickly correct a deviation in process conditions, and which can therefore stably provide a product of constant quality. A substrate processing method for processing a substrate having a metal and an insulating material exposed on its surface in such a manner that a film thickness of the metal, with an exposed surface of the metal as a reference plane, is selectively or preferentially changed, including measuring a change in the film thickness and/or a film property of the metal during and/or immediately after processing, and monitoring processing and adjusting processing conditions based on results of this measurement.
摘要翻译： 提供了可以根据需要测量和监测在基板上形成的膜的厚度和/或性能的基板处理方法和装置，并且可以快速地校正工艺条件的偏差，因此可以稳定地提供恒定品质的产品。 一种基板处理方法，用于处理具有金属和绝缘材料的基板，所述基板以其金属的暴露表面作为基准面的方式选择性地或优先地改变的金属的膜厚度包括 测量处理期间和/或紧随其后的金属的膜厚度和/或膜性质的变化，以及基于该测量结果的监测处理和调整处理条件。
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公开(公告)号：US20050009340A1
公开(公告)日：2005-01-13
申请号：US10885108
申请日：2004-07-07
申请人： Yasuhiko Saijo , Masashi Shimoyama , Hiroshi Yokota , Akihiko Tashiro , Xinming Wang , Daisuke Takagi
发明人： Yasuhiko Saijo , Masashi Shimoyama , Hiroshi Yokota , Akihiko Tashiro , Xinming Wang , Daisuke Takagi
IPC分类号： C23C18/18 , C23C18/16 , C23C18/30 , C23C18/31 , C23C18/50 , H01L21/00 , H01L21/28 , H01L21/288 , H01L21/3205 , H01L21/44 , H01L21/768 , H01L23/52
CPC分类号： H01L21/76874 , C23C18/1855 , C23C18/1893 , H01L21/288 , H01L21/76849
摘要： A capping film serving as an interconnect protective film formed on a surface of interconnect metal on a semiconductor substrate is formed after forming a catalyst layer for electroless plating under low oxygen concentration condition. A method for forming a capping film for protecting a surface of interconnect metal includes preparing a metal catalyst solution containing a metal element nobler than interconnect metal and having dissolved oxygen concentration of 7 ppm or less, bringing said metal catalyst solution into contact with a surface of interconnect metal to form a metal catalyst layer on the surface of the interconnect metal, and performing electroless plating to form a capping film on the surface of the interconnect metal.
摘要翻译： 在低氧浓度条件下形成用于化学镀的催化剂层之后，形成用作半导体衬底上的互连金属表面上的互连保护膜的覆盖膜。 形成用于保护互连金属的表面的封盖膜的方法包括制备含有比互连金属更高的金属元素并且具有7ppm或更低的溶解氧浓度的金属催化剂溶液，使所述金属催化剂溶液与 互连金属，以在互连金属的表面上形成金属催化剂层，并进行化学镀以在互连金属的表面上形成覆盖膜。
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公开(公告)号：US08161608B2
公开(公告)日：2012-04-24
申请号：US12655290
申请日：2009-12-28
申请人： Akihiko Tashiro , Hiroyuki Sasaki
发明人： Akihiko Tashiro , Hiroyuki Sasaki
IPC分类号： H04R17/00
CPC分类号： H03H3/02 , H03H9/19 , Y10T29/42 , Y10T29/49005 , Y10T29/49155 , Y10T29/49156
摘要： To provide a method of manufacturing a quartz-crystal resonator, in which without adding new processes, a desired quartz-crystal piece can be obtained from a quartz-crystal wafer by etching and electrodes can be provided without restraint. When a quartz-crystal piece 10 is formed, etching masks 6 having dummy regions 44, 48 that are provided at two positions corresponding to corner portions on a +X side of the quartz-crystal piece 10 and extend toward a +X axis direction of a wafer W are formed, and when the quartz-crystal piece 10 is formed, etching in groove portions 7 at positions corresponding to the dummy regions 44, 48 is delayed. Accordingly, it is possible to form the quartz-crystal piece 10 without chipped portions at the corner portions in a state where the quartz-crystal piece 10 and the wafer W are connected to and supported by a connection support portion 11.
摘要翻译： 为了提供一种制造石英晶体谐振器的方法，其中在不添加新工艺的情况下，可以通过蚀刻从石英晶片获得期望的石英晶片，并且可以无限制地提供电极。 当形成石英晶片10时，具有虚设区域44,48的蚀刻掩模6，其设置在与石英晶片10的+ X侧的角部对应的两个位置处，并朝向+ 形成晶片W，并且当形成石英晶片10时，延迟对应于虚拟区域44,48的位置处的凹槽部分7中的蚀刻。 因此，在将石英晶片10和晶片W连接并由连接支撑部11支撑的状态下，可以在角部处形成石英晶片10而不具有切口部。
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公开(公告)号：US5549954A
公开(公告)日：1996-08-27
申请号：US296910
申请日：1994-08-31
CPC分类号： B82Y15/00 , G11B5/64 , G11B5/7315 , Y10T428/24355
摘要： A magnetic disc having one or multiple undercoat layers, a continuous thin film magnetic layer or continuous thin film multiple magnetic layers, a protective layer and a lubricant layer sequentially laminated on a non-magnetic disc substrate, which has surface roughness on the surface of the magnetic disc, said surface roughness being such that when the surface roughness is measured by an atomic force microscope or a scanning tunnel microscope, the maximum peak height is from 150 .ANG. to 800 .ANG. based on the height giving the highest frequency in the height distribution of the surface roughness, and the depth (D.sub.0.5) at a bearing ratio of 0.5% from the highest point is from 80 .ANG. to 450 .ANG..
摘要翻译： 具有一个或多个底涂层的磁盘，连续的薄膜磁性层或连续的薄膜多个磁性层，顺序层压在非磁盘基板上的保护层和润滑剂层，其在表面上具有表面粗糙度 磁盘，所述表面粗糙度使得当通过原子力显微镜或扫描隧道显微镜测量表面粗糙度时，基于在高度分布中具有最高频率的高度，最大峰高度为150安培至800安培 表面粗糙度和深度（D0.5）距离最高点的0.5％的轴承比为80安培到450安培。
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公开(公告)号：US20100192340A1
公开(公告)日：2010-08-05
申请号：US12655290
申请日：2009-12-28
申请人： Akihiko Tashiro , Hiroyuki Sasaki
发明人： Akihiko Tashiro , Hiroyuki Sasaki
IPC分类号： H01L41/22
CPC分类号： H03H3/02 , H03H9/19 , Y10T29/42 , Y10T29/49005 , Y10T29/49155 , Y10T29/49156
摘要： To provide a method of manufacturing a quartz-crystal resonator, in which without adding new processes, a desired quartz-crystal piece can be obtained from a quartz-crystal wafer by etching and electrodes can be provided without restraint. When a quartz-crystal piece 10 is formed, etching masks 6 having dummy regions 44, 48 that are provided at two positions corresponding to corner portions on a +X side of the quartz-crystal piece 10 and extend toward a +X axis direction of a wafer W are formed, and when the quartz-crystal piece 10 is formed, etching in groove portions 7 at positions corresponding to the dummy regions 44, 48 is delayed. Accordingly, it is possible to form the quartz-crystal piece 10 without chipped portions at the corner portions in a state where the quartz-crystal piece 10 and the wafer W are connected to and supported by a connection support portion 11.
摘要翻译： 为了提供一种制造石英晶体谐振器的方法，其中在不添加新工艺的情况下，可以通过蚀刻从石英晶片获得期望的石英晶片，并且可以无限制地提供电极。 当形成石英晶片10时，具有虚设区域44,48的蚀刻掩模6，其设置在对应于石英晶片10的+ X侧的角部的两个位置，并向+ 形成晶片W，并且当形成石英晶片10时，延迟对应于虚拟区域44,48的位置处的凹槽部分7中的蚀刻。 因此，在将石英晶片10和晶片W连接并由连接支撑部11支撑的状态下，可以在角部处形成石英晶片10而不具有切口部。
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